libreboot

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commit 3726a2990fb0e0a76b428c2e6db108f45b53a437
parent c2bce312e7a4aa3fc523824e4248ff206d6677eb
Author: Leah Woods <info@minifree.org>
Date:   Sat, 21 May 2016 07:03:40 +0100

GA-G41-ES2L: upgrade to recommended coreboot revision

Diffstat:
resources/libreboot/config/grub/ga-g41m-es2l/cbrevision | 2+-
resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/ga-g41m-es2l/0001-g41-sata.patch | 96-------------------------------------------------------------------------------
resources/libreboot/patch/coreboot/2a6f251f4d8d41d13051ec2c897aea800c07275a/grub/ga-g41m-es2l/0001-g41-sata.patch | 96+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
resources/utilities/coreboot-libre/blobs/coreboot/2a6f251f4d8d41d13051ec2c897aea800c07275a/blobs.list | 52++++++++++++++++++++++++++++++++++++++++++++++++++++
resources/utilities/coreboot-libre/blobs/coreboot/2a6f251f4d8d41d13051ec2c897aea800c07275a/nonblobs.list | 335+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
resources/utilities/coreboot-libre/blobs/coreboot/2a6f251f4d8d41d13051ec2c897aea800c07275a/nonblobs_notes | 15+++++++++++++++
6 files changed, 499 insertions(+), 97 deletions(-)

diff --git a/resources/libreboot/config/grub/ga-g41m-es2l/cbrevision b/resources/libreboot/config/grub/ga-g41m-es2l/cbrevision @@ -1 +1 @@ -2a3434757ef425dbdfedf1fc69e1a033a6e7310d +2a6f251f4d8d41d13051ec2c897aea800c07275a diff --git a/resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/ga-g41m-es2l/0001-g41-sata.patch b/resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/ga-g41m-es2l/0001-g41-sata.patch @@ -1,96 +0,0 @@ -From e1eada0b19f11777ce1ce9e64d99905fbb16bcbd Mon Sep 17 00:00:00 2001 -From: Damien Zammit <damien@zamaudio.com> -Date: Wed, 11 May 2016 19:08:33 +1000 -Subject: [PATCH] mb/gigabyte/ga-g41m-es2l: Fix ACPI IRQ settings for SATA - -Previously, due to a bug in devicetree and incorrect IRQ -settings in ACPI, SATA controller would not initialize -any HDDs in the OS, even though it worked in SeaBIOS. -The devicetree setting is not needed because SATA must -function in "plain" mode on this board, as "combined" mode -does not work at all. - -Change-Id: I0036c4734de00b84cc3d64f38e4b1fd80fd1a25d -Signed-off-by: Damien Zammit <damien@zamaudio.com> ---- - -diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/acpi/x4x_pci_irqs.asl b/src/mainboard/gigabyte/ga-g41m-es2l/acpi/x4x_pci_irqs.asl -index fdfe73d..87719f7 100644 ---- a/src/mainboard/gigabyte/ga-g41m-es2l/acpi/x4x_pci_irqs.asl -+++ b/src/mainboard/gigabyte/ga-g41m-es2l/acpi/x4x_pci_irqs.asl -@@ -22,28 +22,35 @@ - Return (Package() { - /* Internal GFX */ - Package() { 0x0002ffff, 0, 0, 16 }, -+ Package() { 0x0002ffff, 1, 0, 17 }, -+ Package() { 0x0002ffff, 2, 0, 18 }, -+ Package() { 0x0002ffff, 3, 0, 19 }, - /* High Definition Audio 0:1b.0 */ -- Package() { 0x001bffff, 0, 0, 22 }, -+ Package() { 0x001bffff, 0, 0, 16 }, - /* PCIe Root Ports 0:1c.x */ - Package() { 0x001cffff, 0, 0, 16 }, - Package() { 0x001cffff, 1, 0, 17 }, - Package() { 0x001cffff, 2, 0, 18 }, - Package() { 0x001cffff, 3, 0, 19 }, -+ Package() { 0x001cffff, 0, 0, 16 }, -+ Package() { 0x001cffff, 1, 0, 17 }, - /* USB and EHCI 0:1d.x */ - Package() { 0x001dffff, 0, 0, 23 }, - Package() { 0x001dffff, 1, 0, 19 }, - Package() { 0x001dffff, 2, 0, 18 }, - Package() { 0x001dffff, 3, 0, 16 }, -- Package() { 0x001dffff, 0, 0, 23 }, - /* SMBUS/SATA/PATA 0:1f.2, 0:1f.3 */ -- Package() { 0x001fffff, 1, 0, 19 }, -- Package() { 0x001fffff, 1, 0, 19 }, - Package() { 0x001fffff, 0, 0, 18 }, -+ Package() { 0x001fffff, 1, 0, 19 }, -+ Package() { 0x001fffff, 1, 0, 19 }, - }) - } Else { - Return (Package() { - /* Internal GFX */ - Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, -+ Package() { 0x0002ffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, -+ Package() { 0x0002ffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, -+ Package() { 0x0002ffff, 3, \_SB.PCI0.LPCB.LNKD, 0 }, - /* High Definition Audio 0:1b.0 */ - Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - /* PCIe Root Ports 0:1c.x */ -@@ -51,16 +58,17 @@ - Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, - Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKD, 0 }, -+ Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, -+ Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, - /* USB and EHCI 0:1d.x */ - Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKH, 0 }, - Package() { 0x001dffff, 1, \_SB.PCI0.LPCB.LNKD, 0 }, - Package() { 0x001dffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, - Package() { 0x001dffff, 3, \_SB.PCI0.LPCB.LNKA, 0 }, -- Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKH, 0 }, - /* SMBUS/SATA/PATA 0:1f.2, 0:1f.3 */ -- Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKD, 0 }, -- Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKD, 0 }, - Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKC, 0 }, -+ Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKD, 0 }, -+ Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKD, 0 }, - }) - } - } -diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb b/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb -index 3965538..68a3352 100644 ---- a/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb -+++ b/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb -@@ -46,10 +46,8 @@ - register "pirqf_routing" = "0x0b" - register "pirqg_routing" = "0x0b" - register "pirqh_routing" = "0x0b" -- register "ide_legacy_combined" = "0x1" - register "ide_enable_primary" = "0x1" - register "ide_enable_secondary" = "0x0" -- register "sata_ahci" = "0x0" - register "sata_ports_implemented" = "0x3" - register "gpe0_en" = "0x40" - diff --git a/resources/libreboot/patch/coreboot/2a6f251f4d8d41d13051ec2c897aea800c07275a/grub/ga-g41m-es2l/0001-g41-sata.patch b/resources/libreboot/patch/coreboot/2a6f251f4d8d41d13051ec2c897aea800c07275a/grub/ga-g41m-es2l/0001-g41-sata.patch @@ -0,0 +1,96 @@ +From e1eada0b19f11777ce1ce9e64d99905fbb16bcbd Mon Sep 17 00:00:00 2001 +From: Damien Zammit <damien@zamaudio.com> +Date: Wed, 11 May 2016 19:08:33 +1000 +Subject: [PATCH] mb/gigabyte/ga-g41m-es2l: Fix ACPI IRQ settings for SATA + +Previously, due to a bug in devicetree and incorrect IRQ +settings in ACPI, SATA controller would not initialize +any HDDs in the OS, even though it worked in SeaBIOS. +The devicetree setting is not needed because SATA must +function in "plain" mode on this board, as "combined" mode +does not work at all. + +Change-Id: I0036c4734de00b84cc3d64f38e4b1fd80fd1a25d +Signed-off-by: Damien Zammit <damien@zamaudio.com> +--- + +diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/acpi/x4x_pci_irqs.asl b/src/mainboard/gigabyte/ga-g41m-es2l/acpi/x4x_pci_irqs.asl +index fdfe73d..87719f7 100644 +--- a/src/mainboard/gigabyte/ga-g41m-es2l/acpi/x4x_pci_irqs.asl ++++ b/src/mainboard/gigabyte/ga-g41m-es2l/acpi/x4x_pci_irqs.asl +@@ -22,28 +22,35 @@ + Return (Package() { + /* Internal GFX */ + Package() { 0x0002ffff, 0, 0, 16 }, ++ Package() { 0x0002ffff, 1, 0, 17 }, ++ Package() { 0x0002ffff, 2, 0, 18 }, ++ Package() { 0x0002ffff, 3, 0, 19 }, + /* High Definition Audio 0:1b.0 */ +- Package() { 0x001bffff, 0, 0, 22 }, ++ Package() { 0x001bffff, 0, 0, 16 }, + /* PCIe Root Ports 0:1c.x */ + Package() { 0x001cffff, 0, 0, 16 }, + Package() { 0x001cffff, 1, 0, 17 }, + Package() { 0x001cffff, 2, 0, 18 }, + Package() { 0x001cffff, 3, 0, 19 }, ++ Package() { 0x001cffff, 0, 0, 16 }, ++ Package() { 0x001cffff, 1, 0, 17 }, + /* USB and EHCI 0:1d.x */ + Package() { 0x001dffff, 0, 0, 23 }, + Package() { 0x001dffff, 1, 0, 19 }, + Package() { 0x001dffff, 2, 0, 18 }, + Package() { 0x001dffff, 3, 0, 16 }, +- Package() { 0x001dffff, 0, 0, 23 }, + /* SMBUS/SATA/PATA 0:1f.2, 0:1f.3 */ +- Package() { 0x001fffff, 1, 0, 19 }, +- Package() { 0x001fffff, 1, 0, 19 }, + Package() { 0x001fffff, 0, 0, 18 }, ++ Package() { 0x001fffff, 1, 0, 19 }, ++ Package() { 0x001fffff, 1, 0, 19 }, + }) + } Else { + Return (Package() { + /* Internal GFX */ + Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, ++ Package() { 0x0002ffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, ++ Package() { 0x0002ffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, ++ Package() { 0x0002ffff, 3, \_SB.PCI0.LPCB.LNKD, 0 }, + /* High Definition Audio 0:1b.0 */ + Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + /* PCIe Root Ports 0:1c.x */ +@@ -51,16 +58,17 @@ + Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, + Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, + Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKD, 0 }, ++ Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, ++ Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, + /* USB and EHCI 0:1d.x */ + Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKH, 0 }, + Package() { 0x001dffff, 1, \_SB.PCI0.LPCB.LNKD, 0 }, + Package() { 0x001dffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, + Package() { 0x001dffff, 3, \_SB.PCI0.LPCB.LNKA, 0 }, +- Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKH, 0 }, + /* SMBUS/SATA/PATA 0:1f.2, 0:1f.3 */ +- Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKD, 0 }, +- Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKD, 0 }, + Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKC, 0 }, ++ Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKD, 0 }, ++ Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKD, 0 }, + }) + } + } +diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb b/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb +index 3965538..68a3352 100644 +--- a/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb ++++ b/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb +@@ -46,10 +46,8 @@ + register "pirqf_routing" = "0x0b" + register "pirqg_routing" = "0x0b" + register "pirqh_routing" = "0x0b" +- register "ide_legacy_combined" = "0x1" + register "ide_enable_primary" = "0x1" + register "ide_enable_secondary" = "0x0" +- register "sata_ahci" = "0x0" + register "sata_ports_implemented" = "0x3" + register "gpe0_en" = "0x40" + diff --git a/resources/utilities/coreboot-libre/blobs/coreboot/2a6f251f4d8d41d13051ec2c897aea800c07275a/blobs.list b/resources/utilities/coreboot-libre/blobs/coreboot/2a6f251f4d8d41d13051ec2c897aea800c07275a/blobs.list @@ -0,0 +1,52 @@ +src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/F10MicrocodePatch01000085.c +src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/F10MicrocodePatch010000c7.c +src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/F10MicrocodePatch010000c6.c +src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/F10MicrocodePatch010000c8.c +src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevD/F10MicrocodePatch010000d9.c +src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevD/F10MicrocodePatch010000c5.c +src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevE/F10MicrocodePatch010000bf.c +src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrMicrocodePatch06000624_Enc.c +src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrMicrocodePatch0600050D_Enc.c +src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrMicrocodePatch06000425.c +src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnMicrocodePatch0600110F_Enc.c +src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevC/F10MicrocodePatch01000085.c +src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevC/F10MicrocodePatch010000c7.c +src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevC/F10MicrocodePatch010000c6.c +src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevC/F10MicrocodePatch010000c8.c +src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevD/F10MicrocodePatch010000c4.c +src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevD/F10MicrocodePatch010000c5.c +src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevE/F10MicrocodePatch010000bf.c +src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/F14MicrocodePatch0500000B.c +src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/F14MicrocodePatch0500001A.c +src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevC/F10MicrocodePatch01000085.c +src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevC/F10MicrocodePatch010000c6.c +src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevC/F10MicrocodePatch010000c8.c +src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevD/F10MicrocodePatch010000c4.c +src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevD/F10MicrocodePatch010000c5.c +src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevE/F10MicrocodePatch010000bf.c +src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/F12MicrocodePatch03000002.c +src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/F12MicrocodePatch0300000f.c +src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/F12MicrocodePatch0300000e.c +src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevC/F10MicrocodePatch010000c7.c +src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/F10MicrocodePatch01000085.c +src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/F10MicrocodePatch010000b6.c +src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/F10MicrocodePatch01000098.c +src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/F10MicrocodePatch01000086.c +src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevD/F10MicrocodePatch010000c4.c +src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevD/F10MicrocodePatch010000c5.c +src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbId7001MicrocodePatch.c +src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/F14MicrocodePatch05000029.c +src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/F14MicrocodePatch05000119.c +src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/Family/LN/F12NbSmuFirmware.h +src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/Family/0x14/F14NbSmuFirmware.h +src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbSmuFirmwareKB.h +src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbSmuFirmwareTN.h +src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/excel925.h +src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbSamuPatchKB.h +src/vendorcode/amd/cimx/rd890/HotplugFirmware.h +src/cpu/dmp/vortex86ex/dmp_kbd_fw_part1.inc +src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Family/0x14/F14PcieAlibSsdt.h +src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Family/LN/F12PcieAlibSsdt.h +src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/AlibSsdtKB.h +src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieAlibSsdtTNFM2.h +src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieAlibSsdtTNFS1.h diff --git a/resources/utilities/coreboot-libre/blobs/coreboot/2a6f251f4d8d41d13051ec2c897aea800c07275a/nonblobs.list b/resources/utilities/coreboot-libre/blobs/coreboot/2a6f251f4d8d41d13051ec2c897aea800c07275a/nonblobs.list @@ -0,0 +1,335 @@ +payloads/libpayload/curses/PDCurses-3.4/demos/worm.c +payloads/libpayload/curses/PDCurses-3.4/sdl1/deffont.h +payloads/libpayload/curses/PDCurses-3.4/sdl1/deficon.h +payloads/libpayload/curses/PDCurses-3.4/win32/pdckbd.c +payloads/libpayload/curses/PDCurses-3.4/x11/big_icon.xbm +payloads/libpayload/curses/PDCurses-3.4/x11/little_icon.xbm +payloads/libpayload/curses/pdcurses-backend/pdcdisp.c +payloads/libpayload/curses/tinycurses.c +payloads/libpayload/drivers/keyboard.c +payloads/libpayload/drivers/usb/usbmsc.c +payloads/libpayload/tests/cbfs-x86-test.c +payloads/nvramcui/payload.sh +src/cpu/allwinner/a10/raminit.c +src/cpu/amd/geode_gx2/Kconfig +src/cpu/amd/geode_lx/cpureginit.c +src/cpu/amd/geode_lx/Kconfig +src/cpu/amd/model_10xxx/init_cpus.c +src/cpu/amd/model_10xxx/processor_name.c +src/cpu/amd/model_fxx/model_fxx_update_microcode.c +src/cpu/amd/model_fxx/powernow_acpi.c +src/cpu/intel/haswell/acpi.c +src/cpu/intel/microcode/microcode.c +src/cpu/intel/model_2065x/acpi.c +src/cpu/intel/model_206ax/acpi.c +src/cpu/Kconfig +src/cpu/samsung/exynos5250/update-bl1.sh +src/cpu/via/nano/update_ucode.c +src/device/dram/spd_cache.c +src/device/Kconfig +src/device/oprom/yabel/interrupt.c +src/drivers/pc80/mc146818rtc.c +src/drivers/pc80/vga/vga_palette.c +src/Kconfig +src/lib/coreboot_table.c +src/lib/jpeg.c +src/mainboard/advansus/a785e-i/mptable.c +src/mainboard/amd/bimini_fam10/mptable.c +src/mainboard/amd/dinar/buildOpts.c +src/mainboard/amd/dinar/Kconfig +src/mainboard/amd/inagua/Kconfig +src/mainboard/amd/olivehill/mptable.c +src/mainboard/amd/olivehillplus/mptable.c +src/mainboard/amd/parmer/mptable.c +src/mainboard/amd/persimmon/Kconfig +src/mainboard/amd/serengeti_cheetah_fam10/get_bus_conf.c +src/mainboard/amd/south_station/Kconfig +src/mainboard/amd/south_station/mptable.c +src/mainboard/amd/thatcher/mptable.c +src/mainboard/amd/torpedo/Kconfig +src/mainboard/amd/torpedo/mptable.c +src/mainboard/amd/union_station/Kconfig +src/mainboard/amd/union_station/mptable.c +src/mainboard/asrock/e350m1/mptable.c +src/mainboard/asrock/imb-a180/mptable.c +src/mainboard/asus/f2a85-m/mptable.c +src/mainboard/asus/m5a88-v/mptable.c +src/mainboard/avalue/eax-785e/mptable.c +src/mainboard/digitallogic/adl855pc/irq_tables.c +src/mainboard/gigabyte/ga-b75m-d3h/romstage.c +src/mainboard/gizmosphere/gizmo2/Micron_MT41J128M16JT.spd.hex +src/mainboard/gizmosphere/gizmo/mptable.c +src/mainboard/google/bolt/romstage.c +src/mainboard/google/butterfly/hda_verb.c +src/mainboard/google/butterfly/mainboard.c +src/mainboard/google/falco/romstage.c +src/mainboard/google/link/hda_verb.c +src/mainboard/google/link/i915.c +src/mainboard/google/link/romstage.c +src/mainboard/google/panther/lan.c +src/mainboard/google/peach_pit/mainboard.c +src/mainboard/google/peppy/romstage.c +src/mainboard/google/rambi/romstage.c +src/mainboard/google/samus/romstage.c +src/mainboard/google/slippy/romstage.c +src/mainboard/hp/dl165_g6_fam10/get_bus_conf.c +src/mainboard/hp/pavilion_m6_1035dx/mptable.c +src/mainboard/ibase/mb899/cmos.layout +src/mainboard/ibase/mb899/superio_hwm.c +src/mainboard/intel/minnowmax/Kconfig +src/mainboard/intel/wtm2/i915.c +src/mainboard/jetway/nf81-t56n-lf/Kconfig +src/mainboard/kontron/986lcd-m/cmos.layout +src/mainboard/kontron/986lcd-m/mainboard.c +src/mainboard/lenovo/g505s/mptable.c +src/mainboard/lippert/frontrunner-af/Kconfig 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+src/mainboard/intel/sklrvp/spd/spd.c +src/mainboard/intel/kunimitsu/spd/spd.c +src/mainboard/intel/strago/spd/spd.c +src/mainboard/intel/strago/Kconfig +src/mainboard/amd/bettong/mptable.c +src/northbridge/amd/pi/00660F01/Kconfig +util/crossgcc/patches/gcc-5.2.0_riscv.patch +util/xcompile/xcompile +src/northbridge/intel/sandybridge/raminit_mrc.c +src/northbridge/intel/fsp_rangeley/fsp/Kconfig +src/drivers/intel/fsp1_1/car.c +src/mainboard/intel/mohonpeak/Kconfig +src/mainboard/apple/macbookair4_2/early_southbridge.c +src/cpu/intel/fsp_model_406dx/acpi.c +src/northbridge/intel/fsp_sandybridge/fsp/Kconfig +src/drivers/aspeed/common/ast_dram_tables.h +src/drivers/aspeed/common/ast_tables.h +src/mainboard/intel/cougar_canyon2/Kconfig +src/cpu/amd/family_10h-family_15h/processor_name.c +src/cpu/amd/family_10h-family_15h/init_cpus.c +src/cpu/intel/fsp_model_206ax/acpi.c diff --git a/resources/utilities/coreboot-libre/blobs/coreboot/2a6f251f4d8d41d13051ec2c897aea800c07275a/nonblobs_notes b/resources/utilities/coreboot-libre/blobs/coreboot/2a6f251f4d8d41d13051ec2c897aea800c07275a/nonblobs_notes @@ -0,0 +1,15 @@ +.spd.hex files - serial presence detect. These are not blobs +see JEDEC standard or https://en.wikipedia.org/wiki/Serial_presence_detect +These are added to the nonblobs file + +src/northbridge/intel/nehalem/raminit_tables.c" +src/northbridge/intel/sandybridge/raminit_patterns.h +These are used by native raminit for the relevant platforms, and are not blobs + +"src/southbridge/nvidia/mcp55/early_setup_ss.h" \ +"src/southbridge/nvidia/ck804/early_setup_ss.h" \ +"src/southbridge/sis/sis966/early_setup_ss.h" +not blobs + +The text in this file is CC-BY-SA 4.0 or higher. All contributions to it must +be made under the same license.