Author: Francis Rowe <email@example.com>
Date: Thu, 29 Oct 2015 04:03:51 +0000
6 files changed, 11 insertions(+), 11 deletions(-)
diff --git a/docs/future/index.html b/docs/future/index.html
@@ -115,8 +115,8 @@
fchmmr: frame buffer."<br/>
fchmmr: "Others - reserved"<br/>
phcoder: the easiest way is a loop at this position which tries different values and reads (and prints) BSM with them<br/>
- stefanct: fchmmr: he suggest that you change the value and look how BSM reacts to that<br/>
- stefanct: as he pointed out earlier vram size = TOM - BSM<br/>
+ stefanct: fchmmr: they suggest that you change the value and look how BSM reacts to that<br/>
+ stefanct: as they pointed out earlier vram size = TOM - BSM<br/>
stefanct: different values of GMS<br/>
stefanct: phcoder: hm... this could be a hint. look at the text description of TOLUD at page 103<br/>
stefanct: it mentions 64 MB in the text about BSM as well<br/>
diff --git a/docs/future/old.html b/docs/future/old.html
@@ -78,7 +78,7 @@
Reading <b>0xe4361254</b> (address) in Lenovo BIOS always yields FFFFFFFF, even when writing to it (and writing to it doesn't affect brightness controls).
- 'mtjm' on IRC found that the buttons (Fn keys) control /sys/class/backlight/acpi_video0 which has no affect on 61254 (BLC_PWM_CTL). He says
+ 'mtjm' on IRC found that the buttons (Fn keys) control /sys/class/backlight/acpi_video0 which has no affect on 61254 (BLC_PWM_CTL). This person says
intel_backlight has different values and uses the register. devmem2 works, needs checking <b>lspci -vv</b> for where the memory is mapped,
which is different than on coreboot; mtjm found that it was 0xec061254 on his system (X60 Tablet), and the register value is different too.
<b>This is relevant, because we still don't know how backlight controls are actually handled. We got it working by accident. We need to know more.</b>.
@@ -93,7 +93,7 @@
What we want to do is calculate a good value, instead of setting it in devicetree.cb. mtjm says about backlight physics:
it has a light source , uses pulse width modulation (PWM) to turn it on/off, dimming is done by spending less time on.
- <b>Note: this may not be correct; he says his understanding is based on how the Lenote yeeloong works</b>.
+ <b>Note: this may not be correct; this person says that their understanding is based on how the Lenote yeeloong works</b>.
mtjm goes on to say, that the register specifies the frequency used for PWM in its depending on the GPU core frequency, so it
diff --git a/docs/hcl/gm45_remove_me.html b/docs/hcl/gm45_remove_me.html
@@ -540,7 +540,7 @@ DD CC 18 00 11 20 17 00 DD DD 18 00 12 20 17 00
- <i>"One of those engineers loves classic rock music, so he selected 0xBABA"</i>
+ <i>"One of those engineers loves classic rock music, so they selected 0xBABA"</i>
<p>In honour of the song <i>Baba O'Reilly</i> by <i>The Who</i> apparently. We're not making this stuff up...</p>
diff --git a/docs/hcl/index.html b/docs/hcl/index.html
@@ -451,7 +451,7 @@ EndSection
Mono Moosbart is the person who wrote the port for macbook2,1. Referenced below are copies (up to date at the time of writing, 20140630)
- of the pages he wrote when porting coreboot to the macbook2,1. They are included here in case the main site goes down for
+ of the pages that this person wrote when porting coreboot to the macbook2,1. They are included here in case the main site goes down for
whatever reason, since they include a lot of useful information.
@@ -463,7 +463,7 @@ EndSection
<b>Links to wget backups (and the backups themselves) of Mono's pages (see above) removed temporarily. Mono has given me permission to distribute them, but I need to ask
- him to tell me what license these works fall under first. Otherwise, the above URLs should be fine. NOTE TO SELF: REMOVE THIS WHEN DONE</b>
+ this person to tell me what license these works fall under first. Otherwise, the above URLs should be fine. NOTE TO SELF: REMOVE THIS WHEN DONE</b>
diff --git a/docs/hcl/kfsn4-dre.html b/docs/hcl/kfsn4-dre.html
@@ -101,7 +101,7 @@
See <a href="text/kfsn4-dre/bootlog.txt">text/kfsn4-dre/bootlog.txt</a>
- this uses the 'simple' bootblock, while tpearson uses the 'normal'
bootblock, which tpearson suspects may be a possible cause.
- He says that he will look into it.
+ This person says that they will look into it.
<a href="http://review.coreboot.org/gitweb?p=board-status.git;a=blob;f=asus/kfsn4-dre/4.0-10101-g039edeb/2015-06-27T03:59:16Z/config.txt;h=4742905c185a93fbda8eb14322dd82c70641aef0;hb=055f5df4e000a97453dfad6c91c2d06ea22b8545">This config</a> doesn't have the issue.
diff --git a/docs/tasks.html b/docs/tasks.html
@@ -66,7 +66,7 @@
tpearson says: Tyan seems to have done the same thing as Asus did and built a whole lot of custom power control circuitry out of FETs.
- According to him, this will take much effort to reverse engineer.
+ According to this person, this will take much effort to reverse engineer.
IPMI firmware is non-free but optional (for iKVM feature, remote management like Intel ME). Not sure if add-on module or baked in.
@@ -191,7 +191,7 @@
880101121e0cef5df3afda075809e2fbacf68ffe is the commit in coreboot that added native graphics initialization
for GM45. The commit message says that text mode should work. tpearson tested with this revision, and it didn't
work in text mode, so it looks like text mode never worked at all. It could be that it did work before phcoder
- submitted it, but then he made more changes that broke text mode, and didn't realize this. This means that a bisect
+ submitted it, but then they made more changes that broke text mode, and didn't realize this. This means that a bisect
is not possible.
@@ -219,7 +219,7 @@
T400/T500/R400 (tested on T400): UART (serial port) doesn't work. Investigate.
(already tried enabling early h8 dock option. some RE with superiotool is needed).
- - kmalkki has an R400. He says he can be contracted for it. (try to DIY first)
+ - kmalkki has an R400. This person said they can be contracted for it.