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commit 9709332ca52040d75afc258dff36fcbb480a9dcf
parent 892299378727e22a3bc41de06e65a410b71ea243
Author: Leah Rowe <info@minifree.org>
Date:   Fri,  9 Sep 2016 22:25:52 +0100

ga-g41m-es2l: enable use of PCIe x16 port (patches from Damien Zammit)

Diffstat:
resources/libreboot/config/grub/ga-g41m-es2l/cbrevision | 2+-
resources/libreboot/config/grub/ga-g41m-es2l/config | 1+
resources/libreboot/patch/coreboot/55a54f662e2e793306dc7003afbcb82b49db0a8c/grub/ga-g41m-es2l/0001-x4x-gma.c-Add-VESA-native-resolution-mode.patch | 415+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
resources/libreboot/patch/coreboot/55a54f662e2e793306dc7003afbcb82b49db0a8c/grub/ga-g41m-es2l/0002-gigabyte-ga-g41m-es2l-add-VESA-mode-to-Kconfig.patch | 30++++++++++++++++++++++++++++++
resources/libreboot/patch/coreboot/7c2e5396a3d47c64eb5a553fe412aad4c0f8dc1b/grub/ga-g41m-es2l/0001-x4x-gma.c-Add-VESA-native-resolution-mode.patch | 415-------------------------------------------------------------------------------
resources/libreboot/patch/coreboot/7c2e5396a3d47c64eb5a553fe412aad4c0f8dc1b/grub/ga-g41m-es2l/0002-gigabyte-ga-g41m-es2l-add-VESA-mode-to-Kconfig.patch | 30------------------------------
resources/utilities/coreboot-libre/blobs/coreboot/55a54f662e2e793306dc7003afbcb82b49db0a8c/blobs.list | 52++++++++++++++++++++++++++++++++++++++++++++++++++++
resources/utilities/coreboot-libre/blobs/coreboot/55a54f662e2e793306dc7003afbcb82b49db0a8c/nonblobs.list | 335+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
resources/utilities/coreboot-libre/blobs/coreboot/55a54f662e2e793306dc7003afbcb82b49db0a8c/nonblobs_notes | 15+++++++++++++++
9 files changed, 849 insertions(+), 446 deletions(-)

diff --git a/resources/libreboot/config/grub/ga-g41m-es2l/cbrevision b/resources/libreboot/config/grub/ga-g41m-es2l/cbrevision @@ -1 +1 @@ -7c2e5396a3d47c64eb5a553fe412aad4c0f8dc1b +55a54f662e2e793306dc7003afbcb82b49db0a8c diff --git a/resources/libreboot/config/grub/ga-g41m-es2l/config b/resources/libreboot/config/grub/ga-g41m-es2l/config @@ -139,6 +139,7 @@ CONFIG_BOARD_GIGABYTE_GA_G41M_ES2L=y # CONFIG_BOARD_GIGABYTE_MA785GMT is not set # CONFIG_BOARD_GIGABYTE_MA78GM is not set # CONFIG_DRIVERS_PS2_KEYBOARD is not set +CONFIG_DEVICETREE="devicetree.cb" # CONFIG_CONSOLE_POST is not set CONFIG_DRIVERS_UART_8250IO=y CONFIG_CPU_ADDR_BITS=36 diff --git a/resources/libreboot/patch/coreboot/55a54f662e2e793306dc7003afbcb82b49db0a8c/grub/ga-g41m-es2l/0001-x4x-gma.c-Add-VESA-native-resolution-mode.patch b/resources/libreboot/patch/coreboot/55a54f662e2e793306dc7003afbcb82b49db0a8c/grub/ga-g41m-es2l/0001-x4x-gma.c-Add-VESA-native-resolution-mode.patch @@ -0,0 +1,415 @@ +From 9659556d9edbba6c3530ed1d0630add30419210f Mon Sep 17 00:00:00 2001 +From: Arthur Heymans <arthur@aheymans.xyz> +Date: Sun, 4 Sep 2016 16:01:11 +0200 +Subject: [PATCH 1/2] x4x/gma.c: Add VESA native resolution mode + +This patch implements native resolution, VESA mode, on the VGA output of +x4x. + +It relies on EDID to modeset, but has a fallback-mode (640 x 480 @ +60Hz) if this is no EDID could be found. This fallback mode only works in textmode +since in VESA mode some payloads (grub2) rely on VBE info, which is being +generated from an EDID. + +Change-Id: I247ea7171ba3c5dc3b209d00e4dcb2d2069abd75 +Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> +--- + src/northbridge/intel/x4x/gma.c | 282 ++++++++++++++++++++++++++++++++++------ + 1 file changed, 242 insertions(+), 40 deletions(-) + +diff --git a/src/northbridge/intel/x4x/gma.c b/src/northbridge/intel/x4x/gma.c +index 2679026..118f98d 100644 +--- a/src/northbridge/intel/x4x/gma.c ++++ b/src/northbridge/intel/x4x/gma.c +@@ -26,24 +26,68 @@ + #include <cpu/x86/msr.h> + #include <cpu/x86/mtrr.h> + #include <kconfig.h> ++#include <commonlib/helpers.h> + + #include "drivers/intel/gma/i915_reg.h" + #include "chip.h" + #include "x4x.h" + #include <drivers/intel/gma/intel_bios.h> ++#include <drivers/intel/gma/edid.h> + #include <drivers/intel/gma/i915.h> + #include <pc80/vga.h> + #include <pc80/vga_io.h> + ++#define BASE_FREQUENCY 96000 ++ ++static u8 edid_is_null(u8 *edid, u32 edid_size) ++{ ++ u32 i; ++ for (i = 0; i < edid_size; i++) { ++ if (*(edid + i) != 0) ++ return 0; ++ } ++ return 1; ++} + static void intel_gma_init(const struct northbridge_intel_x4x_config *info, +- u8 *mmio) ++ u8 *mmio, u32 physbase, u16 piobase, u32 lfb) + { + ++ + int i; +- u32 hactive, vactive; ++ u8 edid_data[128]; ++ struct edid edid; ++ struct edid_mode *mode; ++ u8 edid_not_found; ++ ++ /* Initialise mode variables for 640 x 480 @ 60Hz */ ++ u32 hactive = 640, vactive = 480; ++ u32 right_border = 0, bottom_border = 0; ++ int hpolarity = 0, vpolarity = 0; ++ u32 hsync = 96, vsync = 2; ++ u32 hblank = 160, vblank = 45; ++ u32 hfront_porch = 16, vfront_porch = 10; ++ u32 target_frequency = 25175; ++ ++ u32 err_most = 0xffffffff; ++ u32 pixel_p1 = 1; ++ u32 pixel_n = 1; ++ u32 pixel_m1 = 1; ++ u32 pixel_m2 = 1; ++ u32 link_frequency = info->gfx.link_frequency_270_mhz ? 270000 : 162000; ++ u32 data_m1; ++ u32 data_n1 = 0x00800000; ++ u32 link_m1; ++ u32 link_n1 = 0x00040000; ++ + + vga_gr_write(0x18, 0); + ++ /* Set up GTT */ ++ for (i = 0; i < 0x1000; i++) { ++ outl((i << 2) | 1, piobase); ++ outl(physbase + (i << 12) + 1, piobase + 4); ++ } ++ + write32(mmio + VGA0, 0x31108); + write32(mmio + VGA1, 0x31406); + +@@ -73,107 +117,258 @@ static void intel_gma_init(const struct northbridge_intel_x4x_config *info, + for (i = 0; i <= 0x18; i++) + vga_cr_write(i, cr[i]); + ++ udelay(1); ++ ++ intel_gmbus_read_edid(mmio + GMBUS0, 2, 0x50, edid_data, 128); ++ intel_gmbus_stop(mmio + GMBUS0); ++ decode_edid(edid_data, ++ sizeof(edid_data), &edid); ++ mode = &edid.mode; ++ ++ + /* Disable screen memory to prevent garbage from appearing. */ + vga_sr_write(1, vga_sr_read(1) | 0x20); + +- hactive = 640; +- vactive = 400; ++ edid_not_found = edid_is_null(edid_data, sizeof(edid_data)); ++ if (!edid_not_found) { ++ printk(BIOS_DEBUG, "EDID is not null"); ++ hactive = edid.x_resolution; ++ vactive = edid.y_resolution; ++ right_border = mode->hborder; ++ bottom_border = mode->vborder; ++ hpolarity = (mode->phsync == '-'); ++ vpolarity = (mode->pvsync == '-'); ++ vsync = mode->vspw; ++ hsync = mode->hspw; ++ vblank = mode->vbl; ++ hblank = mode->hbl; ++ hfront_porch = mode->hso; ++ vfront_porch = mode->vso; ++ target_frequency = mode->pixel_clock; ++ } else ++ printk(BIOS_DEBUG, "EDID is null, using 640 x 480 @ 60Hz mode"); ++ ++ if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) { ++ vga_sr_write(1, 1); ++ vga_sr_write(0x2, 0xf); ++ vga_sr_write(0x3, 0x0); ++ vga_sr_write(0x4, 0xe); ++ vga_gr_write(0, 0x0); ++ vga_gr_write(1, 0x0); ++ vga_gr_write(2, 0x0); ++ vga_gr_write(3, 0x0); ++ vga_gr_write(4, 0x0); ++ vga_gr_write(5, 0x0); ++ vga_gr_write(6, 0x5); ++ vga_gr_write(7, 0xf); ++ vga_gr_write(0x10, 0x1); ++ vga_gr_write(0x11, 0); ++ ++ edid.bytes_per_line = (edid.bytes_per_line + 63) & ~63; ++ ++ write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE ++ | DISPPLANE_BGRX888); ++ write32(mmio + DSPADDR(0), 0); ++ write32(mmio + DSPSTRIDE(0), edid.bytes_per_line); ++ write32(mmio + DSPSURF(0), 0); ++ for (i = 0; i < 0x100; i++) ++ write32(mmio + LGC_PALETTE(0) + 4 * i, i * 0x010101); ++ } else { ++ vga_textmode_init(); ++ } ++ ++ u32 candn, candm1, candm2, candp1; ++ for (candn = 1; candn <= 4; candn++) { ++ for (candm1 = 23; candm1 >= 16; candm1--) { ++ for (candm2 = 11; candm2 >= 5; candm2--) { ++ for (candp1 = 8; candp1 >= 1; candp1--) { ++ u32 m = 5 * (candm1 + 2) + (candm2 + 2); ++ u32 p = candp1 * 10; /* 10 == p2 */ ++ u32 vco = DIV_ROUND_CLOSEST( ++ BASE_FREQUENCY * m, candn + 2); ++ u32 dot = DIV_ROUND_CLOSEST(vco, p); ++ u32 this_err = ABS(dot - target_frequency); ++ if (this_err < err_most) { ++ err_most = this_err; ++ pixel_n = candn; ++ pixel_m1 = candm1; ++ pixel_m2 = candm2; ++ pixel_p1 = candp1; ++ } ++ } ++ } ++ } ++ } ++ ++ if (err_most == 0xffffffff) { ++ printk(BIOS_ERR, "Couldn't find GFX clock divisors\n"); ++ return; ++ } ++ ++ link_m1 = ((uint64_t)link_n1 * mode->pixel_clock) / link_frequency; ++ data_m1 = ((uint64_t)data_n1 * 18 * mode->pixel_clock) ++ / (link_frequency * 8 * 4); ++ ++ printk(BIOS_INFO, "bringing up panel at resolution %d x %d\n", ++ hactive, vactive); ++ printk(BIOS_DEBUG, "Borders %d x %d\n", ++ right_border, bottom_border); ++ printk(BIOS_DEBUG, "Blank %d x %d\n", ++ hblank, vblank); ++ printk(BIOS_DEBUG, "Sync %d x %d\n", ++ hsync, vsync); ++ printk(BIOS_DEBUG, "Front porch %d x %d\n", ++ hfront_porch, vfront_porch); ++ printk(BIOS_DEBUG, (info->gfx.use_spread_spectrum_clock ++ ? "Spread spectrum clock\n" : "DREF clock\n")); ++ printk(BIOS_DEBUG, "Polarities %d, %d\n", ++ hpolarity, vpolarity); ++ printk(BIOS_DEBUG, "Data M1=%d, N1=%d\n", ++ data_m1, data_n1); ++ printk(BIOS_DEBUG, "Link frequency %d kHz\n", ++ link_frequency); ++ printk(BIOS_DEBUG, "Link M1=%d, N1=%d\n", ++ link_m1, link_n1); ++ printk(BIOS_DEBUG, "Pixel N=%d, M1=%d, M2=%d, P1=%d\n", ++ pixel_n, pixel_m1, pixel_m2, pixel_p1); ++ printk(BIOS_DEBUG, "Pixel clock %d kHz\n", ++ BASE_FREQUENCY * (5 * (pixel_m1 + 2) + (pixel_m2 + 2)) / ++ (pixel_n + 2) / (pixel_p1 * 10)); + + mdelay(1); +- write32(mmio + FP0(0), 0x31108); +- write32(mmio + DPLL(0), +- DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL +- | DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 +- | 0x10601 +- ); ++ write32(mmio + FP0(0), (pixel_n << 16) ++ | (pixel_m1 << 8) | pixel_m2); ++ write32(mmio + DPLL(0), DPLL_VCO_ENABLE ++ | DPLL_VGA_MODE_DIS | DPLLB_MODE_DAC_SERIAL ++ | (0x10000 << (pixel_p1 - 1)) ++ | (6 << 9)); ++ + mdelay(1); +- write32(mmio + DPLL(0), +- DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL +- | DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 +- | 0x10601 +- ); ++ write32(mmio + DPLL(0), DPLL_VCO_ENABLE ++ | DPLL_VGA_MODE_DIS | DPLLB_MODE_DAC_SERIAL ++ | (0x10000 << (pixel_p1 - 1)) ++ | (6 << 9)); + + write32(mmio + ADPA, ADPA_DAC_ENABLE + | ADPA_PIPE_A_SELECT + | ADPA_CRT_HOTPLUG_MONITOR_COLOR + | ADPA_CRT_HOTPLUG_ENABLE +- | ADPA_USE_VGA_HVPOLARITY + | ADPA_VSYNC_CNTL_ENABLE + | ADPA_HSYNC_CNTL_ENABLE + | ADPA_DPMS_ON +- ); ++ | (vpolarity ? ADPA_VSYNC_ACTIVE_LOW : ++ ADPA_VSYNC_ACTIVE_HIGH) ++ | (hpolarity ? ADPA_HSYNC_ACTIVE_LOW : ++ ADPA_HSYNC_ACTIVE_HIGH)); + + write32(mmio + HTOTAL(0), +- ((hactive - 1) << 16) ++ ((hactive + right_border + hblank - 1) << 16) + | (hactive - 1)); + write32(mmio + HBLANK(0), +- ((hactive - 1) << 16) +- | (hactive - 1)); ++ ((hactive + right_border + hblank - 1) << 16) ++ | (hactive + right_border - 1)); + write32(mmio + HSYNC(0), +- ((hactive - 1) << 16) +- | (hactive - 1)); ++ ((hactive + right_border + hfront_porch + hsync - 1) << 16) ++ | (hactive + right_border + hfront_porch - 1)); + +- write32(mmio + VTOTAL(0), ((vactive - 1) << 16) +- | (vactive - 1)); +- write32(mmio + VBLANK(0), ((vactive - 1) << 16) ++ write32(mmio + VTOTAL(0), ((vactive + bottom_border + vblank - 1) << 16) + | (vactive - 1)); ++ write32(mmio + VBLANK(0), ((vactive + bottom_border + vblank - 1) << 16) ++ | (vactive + bottom_border - 1)); + write32(mmio + VSYNC(0), +- ((vactive - 1) << 16) +- | (vactive - 1)); ++ ((vactive + bottom_border + vfront_porch + vsync - 1) << 16) ++ | (vactive + bottom_border + vfront_porch - 1)); + + write32(mmio + PIPECONF(0), PIPECONF_DISABLE); + + write32(mmio + PF_WIN_POS(0), 0); +- +- write32(mmio + PIPESRC(0), (639 << 16) | 399); +- write32(mmio + PF_CTL(0),PF_ENABLE | PF_FILTER_MED_3x3); +- write32(mmio + PF_WIN_SZ(0), vactive | (hactive << 16)); +- write32(mmio + PFIT_CONTROL, 0xa0000000); ++ if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) { ++ write32(mmio + PIPESRC(0), ((hactive - 1) << 16) ++ | (vactive - 1)); ++ write32(mmio + PF_CTL(0), 0); ++ write32(mmio + PF_WIN_SZ(0), 0); ++ write32(mmio + PFIT_CONTROL, 0); ++ } else { ++ write32(mmio + PIPESRC(0), (639 << 16) | 399); ++ write32(mmio + PF_CTL(0), PF_ENABLE | PF_FILTER_MED_3x3); ++ write32(mmio + PF_WIN_SZ(0), vactive | (hactive << 16)); ++ write32(mmio + PFIT_CONTROL, 0x80000000); ++ } + + mdelay(1); + ++ write32(mmio + PIPE_DATA_M1(0), 0x7e000000 | data_m1); ++ write32(mmio + PIPE_DATA_N1(0), data_n1); ++ write32(mmio + PIPE_LINK_M1(0), link_m1); ++ write32(mmio + PIPE_LINK_N1(0), link_n1); ++ + write32(mmio + 0x000f000c, 0x00002040); + mdelay(1); + write32(mmio + 0x000f000c, 0x00002050); + write32(mmio + 0x00060100, 0x00044000); + mdelay(1); ++ write32(mmio + PIPECONF(0), PIPECONF_BPP_6); ++ write32(mmio + 0x000f0008, 0x00000040); ++ write32(mmio + 0x000f000c, 0x00022050); ++ write32(mmio + PIPECONF(0), PIPECONF_BPP_6 | PIPECONF_DITHER_EN); + write32(mmio + PIPECONF(0), PIPECONF_ENABLE + | PIPECONF_BPP_6 | PIPECONF_DITHER_EN); + +- write32(mmio + VGACNTRL, 0x0); +- write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE | DISPPLANE_BGRX888); +- mdelay(1); ++ if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) { ++ write32(mmio + VGACNTRL, VGA_DISP_DISABLE); ++ write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE ++ | DISPPLANE_BGRX888); ++ mdelay(1); ++ } else { ++ write32(mmio + VGACNTRL, 0xc4008e); ++ } + + write32(mmio + ADPA, ADPA_DAC_ENABLE + | ADPA_PIPE_A_SELECT + | ADPA_CRT_HOTPLUG_MONITOR_COLOR + | ADPA_CRT_HOTPLUG_ENABLE +- | ADPA_USE_VGA_HVPOLARITY + | ADPA_VSYNC_CNTL_ENABLE + | ADPA_HSYNC_CNTL_ENABLE + | ADPA_DPMS_ON +- ); ++ | (vpolarity ? ADPA_VSYNC_ACTIVE_LOW : ++ ADPA_VSYNC_ACTIVE_HIGH) ++ | (hpolarity ? ADPA_HSYNC_ACTIVE_LOW : ++ ADPA_HSYNC_ACTIVE_HIGH)); + +- vga_textmode_init(); ++ write32(mmio + PP_CONTROL, PANEL_POWER_ON | PANEL_POWER_RESET); + +- /* Enable screen memory. */ ++ /* Enable screen memory. */ + vga_sr_write(1, vga_sr_read(1) & ~0x20); + + /* Clear interrupts. */ + write32(mmio + DEIIR, 0xffffffff); + write32(mmio + SDEIIR, 0xffffffff); ++ ++ if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) { ++ memset((void *) lfb, 0, ++ hactive * vactive * 4); ++ set_vbe_mode_info_valid(&edid, lfb); ++ } + } + + static void native_init(struct device *dev) + { ++ struct resource *lfb_res; ++ struct resource *pio_res; ++ u32 physbase; + struct resource *gtt_res = find_resource(dev, PCI_BASE_ADDRESS_0); + struct northbridge_intel_x4x_config *conf = dev->chip_info; + ++ lfb_res = find_resource(dev, PCI_BASE_ADDRESS_2); ++ pio_res = find_resource(dev, PCI_BASE_ADDRESS_4); ++ physbase = pci_read_config32(dev, 0x5c) & ~0xf; ++ + if (gtt_res && gtt_res->base) { + printk(BIOS_SPEW, + "Initializing VGA without OPROM. MMIO 0x%llx\n", + gtt_res->base); +- intel_gma_init(conf, res2mmio(gtt_res, 0, 0)); ++ intel_gma_init(conf, res2mmio(gtt_res, 0, 0), ++ physbase, pio_res->base, lfb_res->base); + } + + /* Linux relies on VBT for panel info. */ +@@ -182,6 +377,7 @@ static void native_init(struct device *dev) + + static void gma_func0_init(struct device *dev) + { ++ u16 reg16; + u32 reg32; + + /* IGD needs to be Bus Master */ +@@ -189,6 +385,12 @@ static void gma_func0_init(struct device *dev) + reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO; + pci_write_config32(dev, PCI_COMMAND, reg32); + ++ /* configure GMBUSFREQ */ ++ reg16 = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0x2,0)), 0xcc); ++ reg16 &= ~0x1ff; ++ reg16 |= 0xbc; ++ pci_write_config16(dev_find_slot(0, PCI_DEVFN(0x2,0)), 0xcc, reg16); ++ + if (IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT)) + native_init(dev); + else +-- +2.9.3 + diff --git a/resources/libreboot/patch/coreboot/55a54f662e2e793306dc7003afbcb82b49db0a8c/grub/ga-g41m-es2l/0002-gigabyte-ga-g41m-es2l-add-VESA-mode-to-Kconfig.patch b/resources/libreboot/patch/coreboot/55a54f662e2e793306dc7003afbcb82b49db0a8c/grub/ga-g41m-es2l/0002-gigabyte-ga-g41m-es2l-add-VESA-mode-to-Kconfig.patch @@ -0,0 +1,30 @@ +From f9a84edfc672424c9dcaa0a71ad0751c2355c3d0 Mon Sep 17 00:00:00 2001 +From: Arthur Heymans <arthur@aheymans.xyz> +Date: Mon, 5 Sep 2016 12:07:57 +0200 +Subject: [PATCH 2/2] gigabyte/ga-g41m-es2l: add VESA mode to Kconfig + +This patch adds MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG to the +gigabyte/ga-g41m-es2l Kconfig to allow selecting between textmode and +vesamode in menuconfig. + +Change-Id: I84b61118fa0419d49d2498b66029711cdce97576 +Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> +--- + src/mainboard/gigabyte/ga-g41m-es2l/Kconfig | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/Kconfig b/src/mainboard/gigabyte/ga-g41m-es2l/Kconfig +index 6452f4d..281d498 100644 +--- a/src/mainboard/gigabyte/ga-g41m-es2l/Kconfig ++++ b/src/mainboard/gigabyte/ga-g41m-es2l/Kconfig +@@ -26,6 +26,7 @@ config BOARD_SPECIFIC_OPTIONS + select BOARD_ROMSIZE_KB_1024 + select INTEL_EDID + select MAINBOARD_HAS_NATIVE_VGA_INIT ++ select MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG + select PCIEXP_ASPM + select PCIEXP_CLK_PM + select PCIEXP_L1_SUB_STATE +-- +2.9.3 + diff --git a/resources/libreboot/patch/coreboot/7c2e5396a3d47c64eb5a553fe412aad4c0f8dc1b/grub/ga-g41m-es2l/0001-x4x-gma.c-Add-VESA-native-resolution-mode.patch b/resources/libreboot/patch/coreboot/7c2e5396a3d47c64eb5a553fe412aad4c0f8dc1b/grub/ga-g41m-es2l/0001-x4x-gma.c-Add-VESA-native-resolution-mode.patch @@ -1,415 +0,0 @@ -From 9659556d9edbba6c3530ed1d0630add30419210f Mon Sep 17 00:00:00 2001 -From: Arthur Heymans <arthur@aheymans.xyz> -Date: Sun, 4 Sep 2016 16:01:11 +0200 -Subject: [PATCH 1/2] x4x/gma.c: Add VESA native resolution mode - -This patch implements native resolution, VESA mode, on the VGA output of -x4x. - -It relies on EDID to modeset, but has a fallback-mode (640 x 480 @ -60Hz) if this is no EDID could be found. This fallback mode only works in textmode -since in VESA mode some payloads (grub2) rely on VBE info, which is being -generated from an EDID. - -Change-Id: I247ea7171ba3c5dc3b209d00e4dcb2d2069abd75 -Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> ---- - src/northbridge/intel/x4x/gma.c | 282 ++++++++++++++++++++++++++++++++++------ - 1 file changed, 242 insertions(+), 40 deletions(-) - -diff --git a/src/northbridge/intel/x4x/gma.c b/src/northbridge/intel/x4x/gma.c -index 2679026..118f98d 100644 ---- a/src/northbridge/intel/x4x/gma.c -+++ b/src/northbridge/intel/x4x/gma.c -@@ -26,24 +26,68 @@ - #include <cpu/x86/msr.h> - #include <cpu/x86/mtrr.h> - #include <kconfig.h> -+#include <commonlib/helpers.h> - - #include "drivers/intel/gma/i915_reg.h" - #include "chip.h" - #include "x4x.h" - #include <drivers/intel/gma/intel_bios.h> -+#include <drivers/intel/gma/edid.h> - #include <drivers/intel/gma/i915.h> - #include <pc80/vga.h> - #include <pc80/vga_io.h> - -+#define BASE_FREQUENCY 96000 -+ -+static u8 edid_is_null(u8 *edid, u32 edid_size) -+{ -+ u32 i; -+ for (i = 0; i < edid_size; i++) { -+ if (*(edid + i) != 0) -+ return 0; -+ } -+ return 1; -+} - static void intel_gma_init(const struct northbridge_intel_x4x_config *info, -- u8 *mmio) -+ u8 *mmio, u32 physbase, u16 piobase, u32 lfb) - { - -+ - int i; -- u32 hactive, vactive; -+ u8 edid_data[128]; -+ struct edid edid; -+ struct edid_mode *mode; -+ u8 edid_not_found; -+ -+ /* Initialise mode variables for 640 x 480 @ 60Hz */ -+ u32 hactive = 640, vactive = 480; -+ u32 right_border = 0, bottom_border = 0; -+ int hpolarity = 0, vpolarity = 0; -+ u32 hsync = 96, vsync = 2; -+ u32 hblank = 160, vblank = 45; -+ u32 hfront_porch = 16, vfront_porch = 10; -+ u32 target_frequency = 25175; -+ -+ u32 err_most = 0xffffffff; -+ u32 pixel_p1 = 1; -+ u32 pixel_n = 1; -+ u32 pixel_m1 = 1; -+ u32 pixel_m2 = 1; -+ u32 link_frequency = info->gfx.link_frequency_270_mhz ? 270000 : 162000; -+ u32 data_m1; -+ u32 data_n1 = 0x00800000; -+ u32 link_m1; -+ u32 link_n1 = 0x00040000; -+ - - vga_gr_write(0x18, 0); - -+ /* Set up GTT */ -+ for (i = 0; i < 0x1000; i++) { -+ outl((i << 2) | 1, piobase); -+ outl(physbase + (i << 12) + 1, piobase + 4); -+ } -+ - write32(mmio + VGA0, 0x31108); - write32(mmio + VGA1, 0x31406); - -@@ -73,107 +117,258 @@ static void intel_gma_init(const struct northbridge_intel_x4x_config *info, - for (i = 0; i <= 0x18; i++) - vga_cr_write(i, cr[i]); - -+ udelay(1); -+ -+ intel_gmbus_read_edid(mmio + GMBUS0, 2, 0x50, edid_data, 128); -+ intel_gmbus_stop(mmio + GMBUS0); -+ decode_edid(edid_data, -+ sizeof(edid_data), &edid); -+ mode = &edid.mode; -+ -+ - /* Disable screen memory to prevent garbage from appearing. */ - vga_sr_write(1, vga_sr_read(1) | 0x20); - -- hactive = 640; -- vactive = 400; -+ edid_not_found = edid_is_null(edid_data, sizeof(edid_data)); -+ if (!edid_not_found) { -+ printk(BIOS_DEBUG, "EDID is not null"); -+ hactive = edid.x_resolution; -+ vactive = edid.y_resolution; -+ right_border = mode->hborder; -+ bottom_border = mode->vborder; -+ hpolarity = (mode->phsync == '-'); -+ vpolarity = (mode->pvsync == '-'); -+ vsync = mode->vspw; -+ hsync = mode->hspw; -+ vblank = mode->vbl; -+ hblank = mode->hbl; -+ hfront_porch = mode->hso; -+ vfront_porch = mode->vso; -+ target_frequency = mode->pixel_clock; -+ } else -+ printk(BIOS_DEBUG, "EDID is null, using 640 x 480 @ 60Hz mode"); -+ -+ if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) { -+ vga_sr_write(1, 1); -+ vga_sr_write(0x2, 0xf); -+ vga_sr_write(0x3, 0x0); -+ vga_sr_write(0x4, 0xe); -+ vga_gr_write(0, 0x0); -+ vga_gr_write(1, 0x0); -+ vga_gr_write(2, 0x0); -+ vga_gr_write(3, 0x0); -+ vga_gr_write(4, 0x0); -+ vga_gr_write(5, 0x0); -+ vga_gr_write(6, 0x5); -+ vga_gr_write(7, 0xf); -+ vga_gr_write(0x10, 0x1); -+ vga_gr_write(0x11, 0); -+ -+ edid.bytes_per_line = (edid.bytes_per_line + 63) & ~63; -+ -+ write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE -+ | DISPPLANE_BGRX888); -+ write32(mmio + DSPADDR(0), 0); -+ write32(mmio + DSPSTRIDE(0), edid.bytes_per_line); -+ write32(mmio + DSPSURF(0), 0); -+ for (i = 0; i < 0x100; i++) -+ write32(mmio + LGC_PALETTE(0) + 4 * i, i * 0x010101); -+ } else { -+ vga_textmode_init(); -+ } -+ -+ u32 candn, candm1, candm2, candp1; -+ for (candn = 1; candn <= 4; candn++) { -+ for (candm1 = 23; candm1 >= 16; candm1--) { -+ for (candm2 = 11; candm2 >= 5; candm2--) { -+ for (candp1 = 8; candp1 >= 1; candp1--) { -+ u32 m = 5 * (candm1 + 2) + (candm2 + 2); -+ u32 p = candp1 * 10; /* 10 == p2 */ -+ u32 vco = DIV_ROUND_CLOSEST( -+ BASE_FREQUENCY * m, candn + 2); -+ u32 dot = DIV_ROUND_CLOSEST(vco, p); -+ u32 this_err = ABS(dot - target_frequency); -+ if (this_err < err_most) { -+ err_most = this_err; -+ pixel_n = candn; -+ pixel_m1 = candm1; -+ pixel_m2 = candm2; -+ pixel_p1 = candp1; -+ } -+ } -+ } -+ } -+ } -+ -+ if (err_most == 0xffffffff) { -+ printk(BIOS_ERR, "Couldn't find GFX clock divisors\n"); -+ return; -+ } -+ -+ link_m1 = ((uint64_t)link_n1 * mode->pixel_clock) / link_frequency; -+ data_m1 = ((uint64_t)data_n1 * 18 * mode->pixel_clock) -+ / (link_frequency * 8 * 4); -+ -+ printk(BIOS_INFO, "bringing up panel at resolution %d x %d\n", -+ hactive, vactive); -+ printk(BIOS_DEBUG, "Borders %d x %d\n", -+ right_border, bottom_border); -+ printk(BIOS_DEBUG, "Blank %d x %d\n", -+ hblank, vblank); -+ printk(BIOS_DEBUG, "Sync %d x %d\n", -+ hsync, vsync); -+ printk(BIOS_DEBUG, "Front porch %d x %d\n", -+ hfront_porch, vfront_porch); -+ printk(BIOS_DEBUG, (info->gfx.use_spread_spectrum_clock -+ ? "Spread spectrum clock\n" : "DREF clock\n")); -+ printk(BIOS_DEBUG, "Polarities %d, %d\n", -+ hpolarity, vpolarity); -+ printk(BIOS_DEBUG, "Data M1=%d, N1=%d\n", -+ data_m1, data_n1); -+ printk(BIOS_DEBUG, "Link frequency %d kHz\n", -+ link_frequency); -+ printk(BIOS_DEBUG, "Link M1=%d, N1=%d\n", -+ link_m1, link_n1); -+ printk(BIOS_DEBUG, "Pixel N=%d, M1=%d, M2=%d, P1=%d\n", -+ pixel_n, pixel_m1, pixel_m2, pixel_p1); -+ printk(BIOS_DEBUG, "Pixel clock %d kHz\n", -+ BASE_FREQUENCY * (5 * (pixel_m1 + 2) + (pixel_m2 + 2)) / -+ (pixel_n + 2) / (pixel_p1 * 10)); - - mdelay(1); -- write32(mmio + FP0(0), 0x31108); -- write32(mmio + DPLL(0), -- DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL -- | DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 -- | 0x10601 -- ); -+ write32(mmio + FP0(0), (pixel_n << 16) -+ | (pixel_m1 << 8) | pixel_m2); -+ write32(mmio + DPLL(0), DPLL_VCO_ENABLE -+ | DPLL_VGA_MODE_DIS | DPLLB_MODE_DAC_SERIAL -+ | (0x10000 << (pixel_p1 - 1)) -+ | (6 << 9)); -+ - mdelay(1); -- write32(mmio + DPLL(0), -- DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL -- | DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 -- | 0x10601 -- ); -+ write32(mmio + DPLL(0), DPLL_VCO_ENABLE -+ | DPLL_VGA_MODE_DIS | DPLLB_MODE_DAC_SERIAL -+ | (0x10000 << (pixel_p1 - 1)) -+ | (6 << 9)); - - write32(mmio + ADPA, ADPA_DAC_ENABLE - | ADPA_PIPE_A_SELECT - | ADPA_CRT_HOTPLUG_MONITOR_COLOR - | ADPA_CRT_HOTPLUG_ENABLE -- | ADPA_USE_VGA_HVPOLARITY - | ADPA_VSYNC_CNTL_ENABLE - | ADPA_HSYNC_CNTL_ENABLE - | ADPA_DPMS_ON -- ); -+ | (vpolarity ? ADPA_VSYNC_ACTIVE_LOW : -+ ADPA_VSYNC_ACTIVE_HIGH) -+ | (hpolarity ? ADPA_HSYNC_ACTIVE_LOW : -+ ADPA_HSYNC_ACTIVE_HIGH)); - - write32(mmio + HTOTAL(0), -- ((hactive - 1) << 16) -+ ((hactive + right_border + hblank - 1) << 16) - | (hactive - 1)); - write32(mmio + HBLANK(0), -- ((hactive - 1) << 16) -- | (hactive - 1)); -+ ((hactive + right_border + hblank - 1) << 16) -+ | (hactive + right_border - 1)); - write32(mmio + HSYNC(0), -- ((hactive - 1) << 16) -- | (hactive - 1)); -+ ((hactive + right_border + hfront_porch + hsync - 1) << 16) -+ | (hactive + right_border + hfront_porch - 1)); - -- write32(mmio + VTOTAL(0), ((vactive - 1) << 16) -- | (vactive - 1)); -- write32(mmio + VBLANK(0), ((vactive - 1) << 16) -+ write32(mmio + VTOTAL(0), ((vactive + bottom_border + vblank - 1) << 16) - | (vactive - 1)); -+ write32(mmio + VBLANK(0), ((vactive + bottom_border + vblank - 1) << 16) -+ | (vactive + bottom_border - 1)); - write32(mmio + VSYNC(0), -- ((vactive - 1) << 16) -- | (vactive - 1)); -+ ((vactive + bottom_border + vfront_porch + vsync - 1) << 16) -+ | (vactive + bottom_border + vfront_porch - 1)); - - write32(mmio + PIPECONF(0), PIPECONF_DISABLE); - - write32(mmio + PF_WIN_POS(0), 0); -- -- write32(mmio + PIPESRC(0), (639 << 16) | 399); -- write32(mmio + PF_CTL(0),PF_ENABLE | PF_FILTER_MED_3x3); -- write32(mmio + PF_WIN_SZ(0), vactive | (hactive << 16)); -- write32(mmio + PFIT_CONTROL, 0xa0000000); -+ if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) { -+ write32(mmio + PIPESRC(0), ((hactive - 1) << 16) -+ | (vactive - 1)); -+ write32(mmio + PF_CTL(0), 0); -+ write32(mmio + PF_WIN_SZ(0), 0); -+ write32(mmio + PFIT_CONTROL, 0); -+ } else { -+ write32(mmio + PIPESRC(0), (639 << 16) | 399); -+ write32(mmio + PF_CTL(0), PF_ENABLE | PF_FILTER_MED_3x3); -+ write32(mmio + PF_WIN_SZ(0), vactive | (hactive << 16)); -+ write32(mmio + PFIT_CONTROL, 0x80000000); -+ } - - mdelay(1); - -+ write32(mmio + PIPE_DATA_M1(0), 0x7e000000 | data_m1); -+ write32(mmio + PIPE_DATA_N1(0), data_n1); -+ write32(mmio + PIPE_LINK_M1(0), link_m1); -+ write32(mmio + PIPE_LINK_N1(0), link_n1); -+ - write32(mmio + 0x000f000c, 0x00002040); - mdelay(1); - write32(mmio + 0x000f000c, 0x00002050); - write32(mmio + 0x00060100, 0x00044000); - mdelay(1); -+ write32(mmio + PIPECONF(0), PIPECONF_BPP_6); -+ write32(mmio + 0x000f0008, 0x00000040); -+ write32(mmio + 0x000f000c, 0x00022050); -+ write32(mmio + PIPECONF(0), PIPECONF_BPP_6 | PIPECONF_DITHER_EN); - write32(mmio + PIPECONF(0), PIPECONF_ENABLE - | PIPECONF_BPP_6 | PIPECONF_DITHER_EN); - -- write32(mmio + VGACNTRL, 0x0); -- write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE | DISPPLANE_BGRX888); -- mdelay(1); -+ if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) { -+ write32(mmio + VGACNTRL, VGA_DISP_DISABLE); -+ write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE -+ | DISPPLANE_BGRX888); -+ mdelay(1); -+ } else { -+ write32(mmio + VGACNTRL, 0xc4008e); -+ } - - write32(mmio + ADPA, ADPA_DAC_ENABLE - | ADPA_PIPE_A_SELECT - | ADPA_CRT_HOTPLUG_MONITOR_COLOR - | ADPA_CRT_HOTPLUG_ENABLE -- | ADPA_USE_VGA_HVPOLARITY - | ADPA_VSYNC_CNTL_ENABLE - | ADPA_HSYNC_CNTL_ENABLE - | ADPA_DPMS_ON -- ); -+ | (vpolarity ? ADPA_VSYNC_ACTIVE_LOW : -+ ADPA_VSYNC_ACTIVE_HIGH) -+ | (hpolarity ? ADPA_HSYNC_ACTIVE_LOW : -+ ADPA_HSYNC_ACTIVE_HIGH)); - -- vga_textmode_init(); -+ write32(mmio + PP_CONTROL, PANEL_POWER_ON | PANEL_POWER_RESET); - -- /* Enable screen memory. */ -+ /* Enable screen memory. */ - vga_sr_write(1, vga_sr_read(1) & ~0x20); - - /* Clear interrupts. */ - write32(mmio + DEIIR, 0xffffffff); - write32(mmio + SDEIIR, 0xffffffff); -+ -+ if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) { -+ memset((void *) lfb, 0, -+ hactive * vactive * 4); -+ set_vbe_mode_info_valid(&edid, lfb); -+ } - } - - static void native_init(struct device *dev) - { -+ struct resource *lfb_res; -+ struct resource *pio_res; -+ u32 physbase; - struct resource *gtt_res = find_resource(dev, PCI_BASE_ADDRESS_0); - struct northbridge_intel_x4x_config *conf = dev->chip_info; - -+ lfb_res = find_resource(dev, PCI_BASE_ADDRESS_2); -+ pio_res = find_resource(dev, PCI_BASE_ADDRESS_4); -+ physbase = pci_read_config32(dev, 0x5c) & ~0xf; -+ - if (gtt_res && gtt_res->base) { - printk(BIOS_SPEW, - "Initializing VGA without OPROM. MMIO 0x%llx\n", - gtt_res->base); -- intel_gma_init(conf, res2mmio(gtt_res, 0, 0)); -+ intel_gma_init(conf, res2mmio(gtt_res, 0, 0), -+ physbase, pio_res->base, lfb_res->base); - } - - /* Linux relies on VBT for panel info. */ -@@ -182,6 +377,7 @@ static void native_init(struct device *dev) - - static void gma_func0_init(struct device *dev) - { -+ u16 reg16; - u32 reg32; - - /* IGD needs to be Bus Master */ -@@ -189,6 +385,12 @@ static void gma_func0_init(struct device *dev) - reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO; - pci_write_config32(dev, PCI_COMMAND, reg32); - -+ /* configure GMBUSFREQ */ -+ reg16 = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0x2,0)), 0xcc); -+ reg16 &= ~0x1ff; -+ reg16 |= 0xbc; -+ pci_write_config16(dev_find_slot(0, PCI_DEVFN(0x2,0)), 0xcc, reg16); -+ - if (IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT)) - native_init(dev); - else --- -2.9.3 - diff --git a/resources/libreboot/patch/coreboot/7c2e5396a3d47c64eb5a553fe412aad4c0f8dc1b/grub/ga-g41m-es2l/0002-gigabyte-ga-g41m-es2l-add-VESA-mode-to-Kconfig.patch b/resources/libreboot/patch/coreboot/7c2e5396a3d47c64eb5a553fe412aad4c0f8dc1b/grub/ga-g41m-es2l/0002-gigabyte-ga-g41m-es2l-add-VESA-mode-to-Kconfig.patch @@ -1,30 +0,0 @@ -From f9a84edfc672424c9dcaa0a71ad0751c2355c3d0 Mon Sep 17 00:00:00 2001 -From: Arthur Heymans <arthur@aheymans.xyz> -Date: Mon, 5 Sep 2016 12:07:57 +0200 -Subject: [PATCH 2/2] gigabyte/ga-g41m-es2l: add VESA mode to Kconfig - -This patch adds MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG to the -gigabyte/ga-g41m-es2l Kconfig to allow selecting between textmode and -vesamode in menuconfig. - -Change-Id: I84b61118fa0419d49d2498b66029711cdce97576 -Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> ---- - src/mainboard/gigabyte/ga-g41m-es2l/Kconfig | 1 + - 1 file changed, 1 insertion(+) - -diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/Kconfig b/src/mainboard/gigabyte/ga-g41m-es2l/Kconfig -index 6452f4d..281d498 100644 ---- a/src/mainboard/gigabyte/ga-g41m-es2l/Kconfig -+++ b/src/mainboard/gigabyte/ga-g41m-es2l/Kconfig -@@ -26,6 +26,7 @@ config BOARD_SPECIFIC_OPTIONS - select BOARD_ROMSIZE_KB_1024 - select INTEL_EDID - select MAINBOARD_HAS_NATIVE_VGA_INIT -+ select MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG - select PCIEXP_ASPM - select PCIEXP_CLK_PM - select PCIEXP_L1_SUB_STATE --- -2.9.3 - diff --git a/resources/utilities/coreboot-libre/blobs/coreboot/55a54f662e2e793306dc7003afbcb82b49db0a8c/blobs.list b/resources/utilities/coreboot-libre/blobs/coreboot/55a54f662e2e793306dc7003afbcb82b49db0a8c/blobs.list @@ -0,0 +1,52 @@ +src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/F10MicrocodePatch01000085.c +src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/F10MicrocodePatch010000c7.c +src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/F10MicrocodePatch010000c6.c +src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/F10MicrocodePatch010000c8.c +src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevD/F10MicrocodePatch010000d9.c +src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevD/F10MicrocodePatch010000c5.c +src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevE/F10MicrocodePatch010000bf.c +src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrMicrocodePatch06000624_Enc.c +src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrMicrocodePatch0600050D_Enc.c +src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrMicrocodePatch06000425.c +src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnMicrocodePatch0600110F_Enc.c +src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevC/F10MicrocodePatch01000085.c +src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevC/F10MicrocodePatch010000c7.c +src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevC/F10MicrocodePatch010000c6.c +src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevC/F10MicrocodePatch010000c8.c +src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevD/F10MicrocodePatch010000c4.c +src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevD/F10MicrocodePatch010000c5.c +src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevE/F10MicrocodePatch010000bf.c +src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/F14MicrocodePatch0500000B.c +src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/F14MicrocodePatch0500001A.c +src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevC/F10MicrocodePatch01000085.c +src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevC/F10MicrocodePatch010000c6.c +src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevC/F10MicrocodePatch010000c8.c +src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevD/F10MicrocodePatch010000c4.c +src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevD/F10MicrocodePatch010000c5.c +src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevE/F10MicrocodePatch010000bf.c +src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/F12MicrocodePatch03000002.c +src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/F12MicrocodePatch0300000f.c +src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/F12MicrocodePatch0300000e.c +src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevC/F10MicrocodePatch010000c7.c +src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/F10MicrocodePatch01000085.c +src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/F10MicrocodePatch010000b6.c +src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/F10MicrocodePatch01000098.c +src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/F10MicrocodePatch01000086.c +src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevD/F10MicrocodePatch010000c4.c +src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevD/F10MicrocodePatch010000c5.c +src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbId7001MicrocodePatch.c +src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/F14MicrocodePatch05000029.c +src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/F14MicrocodePatch05000119.c +src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/Family/LN/F12NbSmuFirmware.h +src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/Family/0x14/F14NbSmuFirmware.h +src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbSmuFirmwareKB.h +src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbSmuFirmwareTN.h +src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/excel925.h +src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbSamuPatchKB.h +src/vendorcode/amd/cimx/rd890/HotplugFirmware.h +src/cpu/dmp/vortex86ex/dmp_kbd_fw_part1.inc +src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Family/0x14/F14PcieAlibSsdt.h +src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Family/LN/F12PcieAlibSsdt.h +src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/AlibSsdtKB.h +src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieAlibSsdtTNFM2.h +src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieAlibSsdtTNFS1.h diff --git a/resources/utilities/coreboot-libre/blobs/coreboot/55a54f662e2e793306dc7003afbcb82b49db0a8c/nonblobs.list b/resources/utilities/coreboot-libre/blobs/coreboot/55a54f662e2e793306dc7003afbcb82b49db0a8c/nonblobs.list @@ -0,0 +1,335 @@ +payloads/libpayload/curses/PDCurses-3.4/demos/worm.c +payloads/libpayload/curses/PDCurses-3.4/sdl1/deffont.h +payloads/libpayload/curses/PDCurses-3.4/sdl1/deficon.h +payloads/libpayload/curses/PDCurses-3.4/win32/pdckbd.c +payloads/libpayload/curses/PDCurses-3.4/x11/big_icon.xbm +payloads/libpayload/curses/PDCurses-3.4/x11/little_icon.xbm +payloads/libpayload/curses/pdcurses-backend/pdcdisp.c +payloads/libpayload/curses/tinycurses.c +payloads/libpayload/drivers/keyboard.c +payloads/libpayload/drivers/usb/usbmsc.c +payloads/libpayload/tests/cbfs-x86-test.c +payloads/nvramcui/payload.sh +src/cpu/allwinner/a10/raminit.c +src/cpu/amd/geode_gx2/Kconfig +src/cpu/amd/geode_lx/cpureginit.c +src/cpu/amd/geode_lx/Kconfig +src/cpu/amd/model_10xxx/init_cpus.c +src/cpu/amd/model_10xxx/processor_name.c +src/cpu/amd/model_fxx/model_fxx_update_microcode.c +src/cpu/amd/model_fxx/powernow_acpi.c +src/cpu/intel/haswell/acpi.c +src/cpu/intel/microcode/microcode.c +src/cpu/intel/model_2065x/acpi.c +src/cpu/intel/model_206ax/acpi.c +src/cpu/Kconfig +src/cpu/samsung/exynos5250/update-bl1.sh +src/cpu/via/nano/update_ucode.c +src/device/dram/spd_cache.c +src/device/Kconfig +src/device/oprom/yabel/interrupt.c +src/drivers/pc80/mc146818rtc.c +src/drivers/pc80/vga/vga_palette.c +src/Kconfig +src/lib/coreboot_table.c +src/lib/jpeg.c +src/mainboard/advansus/a785e-i/mptable.c +src/mainboard/amd/bimini_fam10/mptable.c +src/mainboard/amd/dinar/buildOpts.c +src/mainboard/amd/dinar/Kconfig +src/mainboard/amd/inagua/Kconfig +src/mainboard/amd/olivehill/mptable.c +src/mainboard/amd/olivehillplus/mptable.c +src/mainboard/amd/parmer/mptable.c +src/mainboard/amd/persimmon/Kconfig +src/mainboard/amd/serengeti_cheetah_fam10/get_bus_conf.c +src/mainboard/amd/south_station/Kconfig +src/mainboard/amd/south_station/mptable.c +src/mainboard/amd/thatcher/mptable.c +src/mainboard/amd/torpedo/Kconfig +src/mainboard/amd/torpedo/mptable.c +src/mainboard/amd/union_station/Kconfig +src/mainboard/amd/union_station/mptable.c +src/mainboard/asrock/e350m1/mptable.c +src/mainboard/asrock/imb-a180/mptable.c +src/mainboard/asus/f2a85-m/mptable.c +src/mainboard/asus/m5a88-v/mptable.c +src/mainboard/avalue/eax-785e/mptable.c +src/mainboard/digitallogic/adl855pc/irq_tables.c +src/mainboard/gigabyte/ga-b75m-d3h/romstage.c +src/mainboard/gizmosphere/gizmo2/Micron_MT41J128M16JT.spd.hex +src/mainboard/gizmosphere/gizmo/mptable.c +src/mainboard/google/bolt/romstage.c +src/mainboard/google/butterfly/hda_verb.c +src/mainboard/google/butterfly/mainboard.c +src/mainboard/google/falco/romstage.c +src/mainboard/google/link/hda_verb.c +src/mainboard/google/link/i915.c +src/mainboard/google/link/romstage.c +src/mainboard/google/panther/lan.c +src/mainboard/google/peach_pit/mainboard.c +src/mainboard/google/peppy/romstage.c +src/mainboard/google/rambi/romstage.c +src/mainboard/google/samus/romstage.c +src/mainboard/google/slippy/romstage.c +src/mainboard/hp/dl165_g6_fam10/get_bus_conf.c +src/mainboard/hp/pavilion_m6_1035dx/mptable.c +src/mainboard/ibase/mb899/cmos.layout +src/mainboard/ibase/mb899/superio_hwm.c +src/mainboard/intel/minnowmax/Kconfig +src/mainboard/intel/wtm2/i915.c +src/mainboard/jetway/nf81-t56n-lf/Kconfig +src/mainboard/kontron/986lcd-m/cmos.layout +src/mainboard/kontron/986lcd-m/mainboard.c +src/mainboard/lenovo/g505s/mptable.c +src/mainboard/lippert/frontrunner-af/Kconfig +src/mainboard/lippert/frontrunner-af/mptable.c +src/mainboard/lippert/toucan-af/Kconfig +src/mainboard/lippert/toucan-af/mptable.c +src/mainboard/msi/ms9652_fam10/get_bus_conf.c +src/mainboard/packardbell/ms2290/mainboard.c +src/mainboard/samsung/lumpy/romstage.c +src/mainboard/siemens/sitemp_g1p1/cmos.layout +src/mainboard/supermicro/h8dmr_fam10/get_bus_conf.c +src/mainboard/supermicro/h8qgi/buildOpts.c +src/mainboard/supermicro/h8qme_fam10/get_bus_conf.c +src/mainboard/supermicro/h8scm/buildOpts.c +src/mainboard/tyan/s2912_fam10/get_bus_conf.c +src/mainboard/tyan/s4880/irq_tables.c +src/mainboard/tyan/s4882/irq_tables.c +src/mainboard/tyan/s8226/buildOpts.c +src/northbridge/amd/agesa/common/common.c +src/northbridge/amd/amdk8/acpi.c +src/northbridge/amd/amdk8/coherent_ht.c +src/northbridge/amd/amdk8/raminit_test.c +src/northbridge/amd/amdmct/mct_ddr3/mcttmrl.c +src/northbridge/amd/amdmct/mct/mctardk3.c +src/northbridge/amd/amdmct/mct/mctardk4.c +src/northbridge/amd/amdmct/mct/mcttmrl.c +src/northbridge/amd/gx2/pll_reset.c +src/northbridge/amd/pi/00730F01/Kconfig +src/northbridge/intel/gm45/raminit_rcomp_calibration.c +src/northbridge/intel/gm45/raminit_read_write_training.c +src/northbridge/intel/haswell/Kconfig +src/northbridge/intel/haswell/raminit.c +src/northbridge/intel/i82830/vga.c +src/northbridge/intel/i945/raminit.c +src/northbridge/intel/nehalem/gma.c +src/northbridge/intel/nehalem/raminit.c +src/northbridge/intel/sandybridge/gma.c +src/northbridge/intel/sandybridge/Kconfig +src/northbridge/intel/sandybridge/raminit.c +src/northbridge/via/cx700/raminit.c +src/northbridge/via/vx800/ide.c +src/northbridge/via/vx800/uma_ram_setting.c +src/northbridge/via/vx900/sata.c +src/soc/intel/baytrail/acpi.c +src/soc/intel/baytrail/Kconfig +src/soc/intel/baytrail/romstage/raminit.c +src/soc/intel/broadwell/acpi.c +src/soc/intel/broadwell/Kconfig +src/soc/intel/broadwell/romstage/raminit.c +src/soc/intel/fsp_baytrail/acpi.c +src/soc/intel/fsp_baytrail/fsp/Kconfig +src/soc/intel/fsp_baytrail/Kconfig +src/soc/qualcomm/ipq806x/Kconfig +src/soc/samsung/exynos5250/clock.c +src/soc/samsung/exynos5420/clock.c +src/southbridge/amd/agesa/hudson/Kconfig +src/southbridge/amd/cimx/sb800/Kconfig +src/southbridge/intel/bd82x6x/Kconfig +src/southbridge/intel/i82801ix/dmi_setup.c +src/southbridge/intel/ibexpeak/Kconfig +src/southbridge/intel/lynxpoint/Kconfig +src/southbridge/intel/sch/Kconfig +src/southbridge/sis/sis966/early_smbus.c +src/southbridge/sis/sis966/ide.c +src/southbridge/sis/sis966/sata.c +src/southbridge/sis/sis966/usb2.c +src/southbridge/sis/sis966/usb.c +src/superio/via/vt1211/vt1211.c +src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10Dmi.c +src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10WheaInitDataTables.c +src/vendorcode/amd/agesa/f10/Proc/Mem/Main/muc.c +src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/cpuF10Dmi.c +src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/cpuF10WheaInitDataTables.c +src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12Dmi.c +src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12WheaInitDataTables.c +src/vendorcode/amd/agesa/f12/Proc/Fch/Hwm/Family/Hudson2/Hudson2HwmLateService.c +src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/Family/LN/F12GfxServices.c +src/vendorcode/amd/agesa/f12/Proc/Mem/Main/muc.c +src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/cpuF10Dmi.c +src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/cpuF10WheaInitDataTables.c +src/vendorcode/amd/agesa/f14/Proc/Mem/Main/muc.c +src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10Dmi.c +src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10WheaInitDataTables.c +src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/cpuF15WheaInitDataTables.c +src/vendorcode/amd/agesa/f15/Proc/Mem/Main/muc.c +src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/OR/mpor3.c +src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/DDR3/mtlrdimm3.c +src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15WheaInitDataTables.c +src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxIntegratedInfoTableTN.c +src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxLibTN.c +src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/muc.c +src/vendorcode/amd/agesa/f15tn/Proc/Mem/Ps/TN/mptn3.c +src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/DDR3/mtlrdimm3.c +src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/cpuF16WheaInitDataTables.c +src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbGfxIntTableV3/GfxLibV3.c +src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbF1TableKB.c +src/vendorcode/amd/agesa/f16kb/Proc/Mem/Main/muc.c +src/vendorcode/amd/agesa/f16kb/Proc/Mem/Ps/KB/mpkb3.c +src/vendorcode/amd/cimx/sb800/SATA.c +src/vendorcode/google/chromeos/build-snow +util/amdtools/example_input/lspci-cb-48G-667MHz-18.2-20090909e +util/amdtools/example_input/lspci-prop-48G-667MHz-18.2 +util/cbfstool/linux_trampoline.c +util/ifdtool/ifdtool.c +util/kconfig/zconf.hash.c_shipped +util/kconfig/zconf.lex.c_shipped +util/kconfig/zconf.tab.c_shipped +util/nvramtool/accessors/layout-bin.c +util/romcc/do_tests.sh +util/romcc/tests/include/linux_console.h +util/romcc/tests/linux_console.h +util/romcc/tests/linux_test5.c +util/romcc/tests/raminit_test6.c +util/romcc/tests/raminit_test7.c +util/romcc/tests/simple_test14.c +util/romcc/tests/simple_test30.c +util/romcc/tests/simple_test38.c +util/romcc/tests/simple_test39.c +util/romcc/tests/simple_test54.c +util/romcc/tests/simple_test59.c +util/romcc/tests/simple_test72.c +util/romcc/tests/simple_test73.c +util/sconfig/lex.yy.c_shipped +util/sconfig/sconfig.tab.c_shipped +util/superiotool/fintek.c +util/superiotool/ite.c +util/superiotool/smsc.c +util/superiotool/winbond.c +src/mainboard/google/slippy/Micron_4KTF25664HZ.spd.hex +src/mainboard/google/falco/Micron_4KTF25664HZ.spd.hex +src/mainboard/google/peppy/Micron_4KTF25664HZ.spd.hex +src/mainboard/google/link/micron_4Gb_1600_1.35v_x16.spd.hex +src/mainboard/google/rambi/spd/micron_1GiB_dimm_MT41K128M16JT-125.spd.hex +src/mainboard/google/rambi/spd/micron_2GiB_dimm_MT41K256M16HA-125.spd.hex +src/mainboard/google/bolt/micron_4Gb_1600_1.35v_x16.spd.hex +src/mainboard/google/link/samsung_4Gb_1600_1.35v_x16.spd.hex +src/mainboard/google/link/elpida_4Gb_1600_x16.spd.hex +src/mainboard/google/slippy/Hynix_HMT425S6AFR6A.spd.hex +src/mainboard/google/falco/Hynix_HMT425S6AFR6A.spd.hex +src/mainboard/google/falco/Elpida_EDJ4216EFBG.spd.hex +src/mainboard/google/rambi/spd/hynix_1GiB_dimm_H5TC2G63FFR-PBA.spd.hex +src/mainboard/google/rambi/spd/hynix_2GiB_dimm_H5TC4G63AFR-PBA.spd.hex +src/mainboard/google/bolt/samsung_4Gb_1600_1.35v_x16.spd.hex +src/mainboard/google/bolt/elpida_4Gb_1600_x16.spd.hex +src/mainboard/google/peppy/Hynix_HMT425S6AFR6A.spd.hex +src/mainboard/google/peppy/Elpida_EDJ4216EFBG.spd.hex +src/mainboard/google/falco/Samsung_M471B5674QH0.spd.hex +src/mainboard/google/samus/spd/empty.spd.hex +src/mainboard/google/samus/spd/elpida_4.spd.hex +src/mainboard/google/samus/spd/hynix_4.spd.hex +src/mainboard/google/samus/spd/elpida_16.spd.hex +src/mainboard/google/samus/spd/hynix_8.spd.hex +src/mainboard/google/samus/spd/hynix_16.spd.hex +src/mainboard/google/samus/spd/samsung_8.spd.hex +src/mainboard/google/samus/spd/elpida_8.spd.hex +src/mainboard/google/samus/spd/samsung_4.spd.hex +src/mainboard/google/auron/spd/Micron_4KTF25664HZ.spd.hex +src/mainboard/google/auron/spd/Elpida_EDJ4216EFBG.spd.hex +src/mainboard/google/auron/spd/Hynix_HMT425S6AFR6A.spd.hex +src/mainboard/google/glados/spd/samsung_dimm_K4E6E304EE-EGCF.spd.hex +src/mainboard/google/auron/spd/empty.spd.hex +src/mainboard/google/cyan/spd/hynix_2GiB_dimm_HMT425S6CFR6A_H5TC4G63CFR.spd.hex +src/mainboard/google/cyan/spd/samsung_2GiB_dimm_K4B4G1646Q-HYK0.spd.hex +src/mainboard/google/cyan/spd/hynix_2GiB_dimm_H5TC4G63AFR-PBA.spd.hex +src/mainboard/google/glados/spd/hynix_dimm_H9CCNNNBLTALAR.spd.hex +src/mainboard/google/glados/spd/empty.spd.hex +src/mainboard/google/glados/spd/hynix_dimm_H9CCNNN8JTBLAR.spd.hex +src/mainboard/intel/sklrvp/spd/empty.spd.hex +src/mainboard/intel/sklrvp/spd/rvp3.spd.hex +src/mainboard/intel/kunimitsu/spd/empty.spd.hex +src/mainboard/intel/kunimitsu/spd/samsung_dimm_K4E8E304EE-EGCE.spd.hex +src/mainboard/intel/strago/spd/hynix_2GiB_dimm_HMT425S6CFR6A_H5TC4G63CFR.spd.hex +src/mainboard/intel/strago/spd/samsung_2GiB_dimm_K4B4G1646Q-HYK0.spd.hex +src/mainboard/intel/strago/spd/hynix_2GiB_dimm_H5TC4G63AFR-PBA.spd.hex +src/mainboard/intel/kunimitsu/spd/hynix_dimm_H9CCNNNBLTALAR-NUD-2G-1866.spd.hex +src/mainboard/intel/kunimitsu/spd/samsung_dimm_K4E8E304EE-EGCF-1G-1866.spd.hex +src/mainboard/intel/kunimitsu/spd/samsung_dimm_K4E6E304EE-EGCF-2G-1866.spd.hex +src/mainboard/intel/kunimitsu/spd/hynix_dimm_H9CCNNN8JTALAR-NUD-1G-1866.spd.hex +src/mainboard/bap/ode_e20XX/BAP_Q7.spd.hex +src/northbridge/intel/nehalem/raminit_tables.c +src/northbridge/intel/sandybridge/raminit_patterns.h +src/southbridge/nvidia/mcp55/early_setup_ss.h +src/southbridge/nvidia/ck804/early_setup_ss.h +src/southbridge/sis/sis966/early_setup_ss.h +util/crossgcc/patches/binutils-2.25_riscv.patch +src/southbridge/amd/pi/hudson/Kconfig +src/drivers/xgi/common/vb_setmode.c +src/drivers/xgi/common/vb_table.h +src/drivers/xgi/common/XGI_main.h +src/mainboard/siemens/mc_tcu3/romstage.c +src/mainboard/siemens/mc_tcu3/lcd_panel.c +src/mainboard/siemens/mc_tcu3/modhwinfo.c +src/mainboard/pcengines/apu1/Kconfig +src/mainboard/asus/kfsn4-dre/get_bus_conf.c +src/mainboard/google/samus/spd/spd.c +src/mainboard/hp/abm/mptable.c +src/northbridge/amd/pi/00630F01/Kconfig +src/cpu/amd/microcode/microcode.c +src/lib/tlcl_structures.h +util/rockchip/make_idb.py +util/autoport/readme.md +util/bimgtool/bimgtool.c +util/cbfstool/fmd_parser.c_shipped +util/cbfstool/fmd_scanner.c_shipped +Documentation/CorebootBuildingGuide.tex +Documentation/hypertransport.svg +Documentation/codeflow.svg +src/soc/broadcom/cygnus/ddr_init.c +src/soc/broadcom/cygnus/ddr_init_table.c +src/soc/qualcomm/ipq806x/lcc.c +src/soc/intel/braswell/acpi.c +src/soc/intel/braswell/Kconfig +src/vendorcode/amd/pi/Kconfig +src/drivers/intel/fsp1_1/Kconfig +src/drivers/intel/fsp1_1/fsp_gop.c +src/drivers/i2c/ww_ring/ww_ring_programs.c +src/mainboard/google/auron/spd/spd.c +src/mainboard/google/jecht/lan.c +src/mainboard/gigabyte/ga-b75m-d3v/romstage.c +src/mainboard/amd/lamar/Kconfig +payloads/external/GRUB2/Kconfig +payloads/external/FILO/Kconfig +payloads/external/SeaBIOS/Kconfig +src/soc/intel/common/fsp_ramstage.c +src/soc/intel/skylake/Kconfig +src/soc/intel/braswell/gpio.c +src/soc/nvidia/tegra210/Kconfig +src/soc/nvidia/tegra210/mtc.c +src/southbridge/intel/common/firmware/Kconfig +src/mainboard/google/cyan/spd/spd.c +src/mainboard/google/cyan/Kconfig +src/mainboard/google/glados/spd/spd.c +src/mainboard/intel/sklrvp/spd/spd.c +src/mainboard/intel/kunimitsu/spd/spd.c +src/mainboard/intel/strago/spd/spd.c +src/mainboard/intel/strago/Kconfig +src/mainboard/amd/bettong/mptable.c +src/northbridge/amd/pi/00660F01/Kconfig +util/crossgcc/patches/gcc-5.2.0_riscv.patch +util/xcompile/xcompile +src/northbridge/intel/sandybridge/raminit_mrc.c +src/northbridge/intel/fsp_rangeley/fsp/Kconfig +src/drivers/intel/fsp1_1/car.c +src/mainboard/intel/mohonpeak/Kconfig +src/mainboard/apple/macbookair4_2/early_southbridge.c +src/cpu/intel/fsp_model_406dx/acpi.c +src/northbridge/intel/fsp_sandybridge/fsp/Kconfig +src/drivers/aspeed/common/ast_dram_tables.h +src/drivers/aspeed/common/ast_tables.h +src/mainboard/intel/cougar_canyon2/Kconfig +src/cpu/amd/family_10h-family_15h/processor_name.c +src/cpu/amd/family_10h-family_15h/init_cpus.c +src/cpu/intel/fsp_model_206ax/acpi.c diff --git a/resources/utilities/coreboot-libre/blobs/coreboot/55a54f662e2e793306dc7003afbcb82b49db0a8c/nonblobs_notes b/resources/utilities/coreboot-libre/blobs/coreboot/55a54f662e2e793306dc7003afbcb82b49db0a8c/nonblobs_notes @@ -0,0 +1,15 @@ +.spd.hex files - serial presence detect. These are not blobs +see JEDEC standard or https://en.wikipedia.org/wiki/Serial_presence_detect +These are added to the nonblobs file + +src/northbridge/intel/nehalem/raminit_tables.c" +src/northbridge/intel/sandybridge/raminit_patterns.h +These are used by native raminit for the relevant platforms, and are not blobs + +"src/southbridge/nvidia/mcp55/early_setup_ss.h" \ +"src/southbridge/nvidia/ck804/early_setup_ss.h" \ +"src/southbridge/sis/sis966/early_setup_ss.h" +not blobs + +The text in this file is CC-BY-SA 4.0 or higher. All contributions to it must +be made under the same license.