libreboot

Unnamed repository; edit this file 'description' to name the repository.
Log | Files | Refs | README

commit c679b19f0b0d95f587b3836c7bf867a932d3df28
parent 3ca295f25340344f5d42164bd134dbb9f5b0ff4c
Author: Leah Rowe <info@minifree.org>
Date:   Mon, 22 Aug 2016 10:22:04 +0100

actually add the documentation directory. (I forgot git add in last commit)

Diffstat:
docs/archive_old.html | 1531+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
docs/constants.texi | 2++
docs/css/main.css | 80+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
docs/depthcharge/index.html | 362+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
docs/future/coreboot_native_3.12_bug.tar.gz | 0
docs/future/donotusethis_macbook_acpi.diff | 28++++++++++++++++++++++++++++
docs/future/dumps/5320_7c0000_gma.c | 519+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
docs/future/dumps/5885_logs.tar.gz | 0
docs/future/dumps/5885_logs_2.tar.gz | 0
docs/future/dumps/5927_2.tar.gz | 0
docs/future/dumps/5927_3.tar.gz | 0
docs/future/dumps/5927_5.tar.gz | 0
docs/future/dumps/5927_6.tar.gz | 0
docs/future/dumps/5927_7.tar.gz | 0
docs/future/dumps/5927_cbmemc | 1442+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
docs/future/dumps/5927_config | 441+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
docs/future/dumps/5927_crashdump | 77+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
docs/future/dumps/coreboot_5296_oprom_grub_cbmemc | 1436+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
docs/future/dumps/coreboot_5926_oprom_grub_config | 449+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
docs/future/dumps/grub.cfg | 38++++++++++++++++++++++++++++++++++++++
docs/future/dumps/grub_memdisk_serial.cfg | 10++++++++++
docs/future/dumps/kernel312_irc | 1590+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
docs/future/dumps/logs-t400-bios2.02-ec1.01/biosdecode.log | 24++++++++++++++++++++++++
docs/future/dumps/logs-t400-bios2.02-ec1.01/codec#0 | 208+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
docs/future/dumps/logs-t400-bios2.02-ec1.01/cpuinfo.log | 52++++++++++++++++++++++++++++++++++++++++++++++++++++
docs/future/dumps/logs-t400-bios2.02-ec1.01/dmesg.log | 1042+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
docs/future/dumps/logs-t400-bios2.02-ec1.01/dmidecode.log | 611+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
docs/future/dumps/logs-t400-bios2.02-ec1.01/ectool.log | 19+++++++++++++++++++
docs/future/dumps/logs-t400-bios2.02-ec1.01/flashrom_info.log | 1+
docs/future/dumps/logs-t400-bios2.02-ec1.01/flashrom_read.log | 1+
docs/future/dumps/logs-t400-bios2.02-ec1.01/inteltool.log | 4406+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
docs/future/dumps/logs-t400-bios2.02-ec1.01/lspci.log | 2696+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
docs/future/dumps/logs-t400-bios2.02-ec1.01/lspnp.log | 1+
docs/future/dumps/logs-t400-bios2.02-ec1.01/lsusb.log | 820+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
docs/future/dumps/logs-t400-bios2.02-ec1.01/msrtool.log | 25+++++++++++++++++++++++++
docs/future/dumps/logs-t400-bios2.02-ec1.01/nvramtool.log | 16++++++++++++++++
docs/future/dumps/logs-t400-bios2.02-ec1.01/pin_hwC0D0 | 8++++++++
docs/future/dumps/logs-t400-bios2.02-ec1.01/superiotool.log | 170+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
docs/future/dumps/logs-t400-bios2.02-ec1.01/t400_flashrom_read_with_bbb.txt | 291++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
docs/future/dumps/logs-t400-bios2.02-ec1.01/t400_flashrom_write_with_bbb.txt | 294+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
docs/future/dumps/pte_x60_6718/dmesg | 2071+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
docs/future/dumps/pte_x60_6718/kern.log | 2026+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
docs/future/dumps/t500_x200_descriptor/descriptor_diff_t500_x200.txt | 3366+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
docs/future/dumps/t500_x200_descriptor/gbe_diff_t500_x200.txt | 68++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
docs/future/dumps/t500log/biosdecode.log | 24++++++++++++++++++++++++
docs/future/dumps/t500log/codec#0 | 208+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
docs/future/dumps/t500log/cpuinfo.log | 58++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
docs/future/dumps/t500log/dmesg.log | 1062+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
docs/future/dumps/t500log/dmidecode.log | 651+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
docs/future/dumps/t500log/ectool.log | 19+++++++++++++++++++
docs/future/dumps/t500log/flashrom_info.log | 118+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
docs/future/dumps/t500log/flashrom_read.log | 123+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
docs/future/dumps/t500log/flashrom_write.log | 119+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
docs/future/dumps/t500log/inteltool.log | 3373+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
docs/future/dumps/t500log/lspci.log | 2120+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
docs/future/dumps/t500log/lspnp.log | 1+
docs/future/dumps/t500log/lsusb.log | 614+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
docs/future/dumps/t500log/msrtool.log | 29+++++++++++++++++++++++++++++
docs/future/dumps/t500log/nvramtool.log | 16++++++++++++++++
docs/future/dumps/t500log/pin_hwC0D0 | 8++++++++
docs/future/dumps/t500log/superiotool.log | 170+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
docs/future/dumps/x | 1442+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
docs/future/dumps/x60_5893_native.tar.gz | 0
docs/future/dumps/x60_5893_native_crashdump | 77+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
docs/future/dumps/x60_5893_vbios.tar.gz | 0
docs/future/dumps/x60_lspcixxxvvnn_5927_19 | 809+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
docs/future/dumps/x60_lspcixxxvvnn_6717_1 | 810+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
docs/future/dumps/x60_lspcixxxvvnn_factory | 842+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
docs/future/gnutoo_fallback_patch | 182+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
docs/future/index.html | 599+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
docs/future/old.html | 319+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
docs/gfdl-1.3.txt | 451+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
docs/git/index.html | 622+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
docs/gnulinux/configuring_parabola.html | 884+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
docs/gnulinux/encrypted_parabola.html | 854+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
docs/gnulinux/encrypted_trisquel.html | 498+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
docs/gnulinux/grub_boot_installer.html | 312+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
docs/gnulinux/grub_cbfs.html | 376+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
docs/gnulinux/grub_config.html | 223+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
docs/gnulinux/index.html | 97+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
docs/grub/index.html | 190+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
docs/hardware/index.html | 82+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
docs/hardware/t60_heatsink.html | 171+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
docs/hardware/t60_lcd_15.html | 128+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
docs/hardware/x60_heatsink.html | 187+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
docs/hardware/x60_keyboard.html | 91+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
docs/hardware/x60_lcd_change.html | 83+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
docs/hcl/c201.html | 262+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
docs/hcl/d510mo.html | 82+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
docs/hcl/ga-g41m-es2l.html | 92+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
docs/hcl/gm45_lcd.html | 366+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
docs/hcl/gm45_remove_me.html | 693+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
docs/hcl/hwdumps/x200/biosdecode.err.log | 0
docs/hcl/hwdumps/x200/biosdecode.log | 24++++++++++++++++++++++++
docs/hcl/hwdumps/x200/codec#0 | 208+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
docs/hcl/hwdumps/x200/cpuinfo.err.log | 0
docs/hcl/hwdumps/x200/cpuinfo.log | 52++++++++++++++++++++++++++++++++++++++++++++++++++++
docs/hcl/hwdumps/x200/dmesg.err.log | 0
docs/hcl/hwdumps/x200/dmesg.log | 1066+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
docs/hcl/hwdumps/x200/dmidecode.err.log | 0
docs/hcl/hwdumps/x200/dmidecode.log | 587+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
docs/hcl/hwdumps/x200/ectool.err.log | 1+
docs/hcl/hwdumps/x200/ectool.log | 0
docs/hcl/hwdumps/x200/flashrom_info.err.log | 14++++++++++++++
docs/hcl/hwdumps/x200/flashrom_info.log | 289++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
docs/hcl/hwdumps/x200/flashrom_read.err.log | 16++++++++++++++++
docs/hcl/hwdumps/x200/flashrom_read.log | 292+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
docs/hcl/hwdumps/x200/input_bustypes.log | 11+++++++++++
docs/hcl/hwdumps/x200/inteltool.err.log | 1+
docs/hcl/hwdumps/x200/inteltool.log | 0
docs/hcl/hwdumps/x200/ioports.err.log | 0
docs/hcl/hwdumps/x200/ioports.log | 60++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
docs/hcl/hwdumps/x200/lspci.err.log | 0
docs/hcl/hwdumps/x200/lspci.log | 2287+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
docs/hcl/hwdumps/x200/lspnp.err.log | 1+
docs/hcl/hwdumps/x200/lspnp.log | 0
docs/hcl/hwdumps/x200/lsusb.err.log | 0
docs/hcl/hwdumps/x200/lsusb.log | 820+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
docs/hcl/hwdumps/x200/msrtool.err.log | 1+
docs/hcl/hwdumps/x200/msrtool.log | 0
docs/hcl/hwdumps/x200/nvramtool.err.log | 1+
docs/hcl/hwdumps/x200/nvramtool.log | 0
docs/hcl/hwdumps/x200/pin_hwC0D0 | 8++++++++
docs/hcl/hwdumps/x200/superiotool.err.log | 1+
docs/hcl/hwdumps/x200/superiotool.log | 0
docs/hcl/images/x200/gpio33_location.jpg | 0
docs/hcl/index.html | 682+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
docs/hcl/kcma-d8.html | 186+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
docs/hcl/kfsn4-dre.html | 164+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
docs/hcl/kgpe-d16.html | 310+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
docs/hcl/r400.html | 140+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
docs/hcl/t400.html | 161+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
docs/hcl/t500.html | 191+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
docs/hcl/text/kfsn4-dre/bootlog.txt | 3871+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
docs/hcl/text/x200s/cblog00.txt | 196+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
docs/hcl/text/x200s/cblog01.txt | 1569+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
docs/hcl/text/x200s/cblog02.txt | 77+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
docs/hcl/text/x200s/cblog03.txt | 158+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
docs/hcl/x200.html | 391+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
docs/images/d510mo/d510mo.jpg | 0
docs/images/ga-g41m-es2l/ga-g41m-es2l.jpg | 0
docs/images/t60_dev/.htaccess | 2++
docs/images/t60_dev/0001.JPG | 0
docs/images/t60_dev/0002.JPG | 0
docs/images/t60_dev/0003.JPG | 0
docs/images/t60_dev/0004.JPG | 0
docs/images/t60_dev/0005.JPG | 0
docs/images/t60_dev/0006.JPG | 0
docs/images/t60_dev/0007.JPG | 0
docs/images/t60_dev/0008.JPG | 0
docs/images/t60_dev/0009.JPG | 0
docs/images/t60_dev/0010.JPG | 0
docs/images/t60_dev/0011.JPG | 0
docs/images/t60_dev/0012.JPG | 0
docs/images/t60_dev/0013.JPG | 0
docs/images/t60_dev/0014.JPG | 0
docs/images/t60_dev/0015.JPG | 0
docs/images/t60_dev/0016.JPG | 0
docs/images/t60_dev/0017.JPG | 0
docs/images/t60_dev/0018.JPG | 0
docs/images/t60_dev/0019.JPG | 0
docs/images/t60_dev/0020.JPG | 0
docs/images/t60_dev/0021.JPG | 0
docs/images/t60_dev/0022.JPG | 0
docs/images/t60_dev/0023.JPG | 0
docs/images/t60_dev/0024.JPG | 0
docs/images/t60_dev/0025.JPG | 0
docs/images/t60_dev/0026.JPG | 0
docs/images/t60_dev/0027.JPG | 0
docs/images/t60_dev/0028.JPG | 0
docs/images/t60_dev/0029.JPG | 0
docs/images/t60_dev/0030.JPG | 0
docs/images/t60_dev/0031.JPG | 0
docs/images/t60_dev/0032.JPG | 0
docs/images/t60_dev/0033.JPG | 0
docs/images/t60_dev/0039.JPG | 0
docs/images/t60_dev/0040.JPG | 0
docs/images/t60_dev/0041.JPG | 0
docs/images/t60_dev/0042.JPG | 0
docs/images/t60_dev/0043.JPG | 0
docs/images/t60_dev/0044.JPG | 0
docs/images/t60_dev/0045.JPG | 0
docs/images/t60_dev/0046.JPG | 0
docs/images/t60_dev/0047.JPG | 0
docs/images/t60_dev/0048.JPG | 0
docs/images/t60_dev/0049.JPG | 0
docs/images/t60_dev/0050.JPG | 0
docs/images/t60_dev/0051.JPG | 0
docs/images/t60_dev/0052.JPG | 0
docs/images/t60_dev/0053.JPG | 0
docs/images/t60_dev/0054.JPG | 0
docs/images/t60_dev/0055.JPG | 0
docs/images/t60_dev/0056.JPG | 0
docs/images/t60_dev/0057.JPG | 0
docs/images/t60_dev/0058.JPG | 0
docs/images/t60_dev/0059.JPG | 0
docs/images/t60_dev/0060.JPG | 0
docs/images/t60_dev/0061.JPG | 0
docs/images/t60_dev/0062.JPG | 0
docs/images/t60_dev/0063.JPG | 0
docs/images/t60_dev/0064.JPG | 0
docs/images/t60_dev/0065.JPG | 0
docs/images/t60_dev/0066.JPG | 0
docs/images/t60_dev/0068.JPG | 0
docs/images/t60_dev/0069.JPG | 0
docs/images/t60_dev/0070.JPG | 0
docs/images/t60_dev/0071.JPG | 0
docs/images/t60_dev/0072.JPG | 0
docs/images/t60_dev/0073.JPG | 0
docs/images/t60_dev/0074.JPG | 0
docs/images/t60_dev/t60_unbrick.jpg | 0
docs/images/x60_heatsink/0000.jpg | 0
docs/images/x60_heatsink/0001.jpg | 0
docs/images/x60_heatsink/0002.jpg | 0
docs/images/x60_heatsink/0003.jpg | 0
docs/images/x60_heatsink/0004.jpg | 0
docs/images/x60_heatsink/0005.jpg | 0
docs/images/x60_heatsink/0006.jpg | 0
docs/images/x60_heatsink/0007.jpg | 0
docs/images/x60_heatsink/0008.jpg | 0
docs/images/x60_heatsink/0009.jpg | 0
docs/images/x60_heatsink/0010.jpg | 0
docs/images/x60_heatsink/0011.jpg | 0
docs/images/x60_heatsink/0012.jpg | 0
docs/images/x60_heatsink/0013.jpg | 0
docs/images/x60_heatsink/0014.jpg | 0
docs/images/x60_heatsink/0015.jpg | 0
docs/images/x60_heatsink/0016.jpg | 0
docs/images/x60_heatsink/0017.jpg | 0
docs/images/x60_heatsink/0018.jpg | 0
docs/images/x60_keyboard/1.JPG | 0
docs/images/x60_keyboard/2.JPG | 0
docs/images/x60_keyboard/3.JPG | 0
docs/images/x60_keyboard/4.JPG | 0
docs/images/x60_keyboard/5.JPG | 0
docs/images/x60_lcd_change/0001.JPG | 0
docs/images/x60_lcd_change/0002.JPG | 0
docs/images/x60_lcd_change/0003.JPG | 0
docs/images/x60_lcd_change/0004.JPG | 0
docs/images/x60_lcd_change/0005.JPG | 0
docs/images/x60_lcd_change/0006.JPG | 0
docs/images/x60_lcd_change/0007.JPG | 0
docs/images/x60_security/0000.jpg | 0
docs/images/x60_security/0000_bluetooth.jpg | 0
docs/images/x60_security/0000_bluetooth0.jpg | 0
docs/images/x60_security/0000_simcard0.jpg | 0
docs/images/x60_security/0000_simcard1.jpg | 0
docs/images/x60_security/0001.jpg | 0
docs/images/x60_security/0001_microphone.jpg | 0
docs/images/x60_security/0001_modem.jpg | 0
docs/images/x60_security/0001_overview.jpg | 0
docs/images/x60_security/0001_speaker.jpg | 0
docs/images/x60_security/0001_wlan_wwan.jpg | 0
docs/images/x60_security/0002.jpg | 0
docs/images/x60_security/0003.jpg | 0
docs/images/x60_security/0004.jpg | 0
docs/images/x60_unbrick/0000.jpg | 0
docs/images/x60_unbrick/0001.jpg | 0
docs/images/x60_unbrick/0002.jpg | 0
docs/images/x60_unbrick/0003.jpg | 0
docs/images/x60_unbrick/0004.jpg | 0
docs/images/x60_unbrick/0005.jpg | 0
docs/images/x60_unbrick/0006.jpg | 0
docs/images/x60_unbrick/0007.jpg | 0
docs/images/x60_unbrick/0008.jpg | 0
docs/images/x60_unbrick/0009.jpg | 0
docs/images/x60_unbrick/0010.jpg | 0
docs/images/x60_unbrick/0011.jpg | 0
docs/images/x60_unbrick/0012.jpg | 0
docs/images/x60_unbrick/0013.jpg | 0
docs/images/x60_unbrick/0014.jpg | 0
docs/images/x60_unbrick/0015.jpg | 0
docs/images/x60_unbrick/0016.jpg | 0
docs/images/x60_unbrick/0017.jpg | 0
docs/images/x60_unbrick/0026.jpg | 0
docs/images/x60_unbrick/0027.jpg | 0
docs/images/x60_unbrick/0028.jpg | 0
docs/images/x60_unbrick/0029.jpg | 0
docs/images/x60_unbrick/0030.jpg | 0
docs/images/x60_unbrick/0031.jpg | 0
docs/images/x60_unbrick/0032.jpg | 0
docs/images/x60_unbrick/0033.jpg | 0
docs/images/x60_unbrick/0034.jpg | 0
docs/images/x60_unbrick/0035.jpg | 0
docs/images/x60_unbrick/0036.jpg | 0
docs/images/x60_unbrick/0037.jpg | 0
docs/images/x60_unbrick/0038.jpg | 0
docs/images/x60_unbrick/0039.jpg | 0
docs/images/x60_unbrick/0040.jpg | 0
docs/images/x60_unbrick/0041.jpg | 0
docs/images/x60_unbrick/0042.jpg | 0
docs/images/x60_unbrick/0043.jpg | 0
docs/images/x60_unbrick/0044.jpg | 0
docs/images/x60_unbrick/0045.jpg | 0
docs/images/x60_unbrick/0046.jpg | 0
docs/images/x60_unbrick/0047.jpg | 0
docs/images/x60_unbrick/0048.jpg | 0
docs/images/x60_unbrick/0049.jpg | 0
docs/images/x60t_unbrick/.htaccess | 2++
docs/images/x60t_unbrick/0000.JPG | 0
docs/images/x60t_unbrick/0001.JPG | 0
docs/images/x60t_unbrick/0002.JPG | 0
docs/images/x60t_unbrick/0003.JPG | 0
docs/images/x60t_unbrick/0004.JPG | 0
docs/images/x60t_unbrick/0005.JPG | 0
docs/images/x60t_unbrick/0006.JPG | 0
docs/images/x60t_unbrick/0007.JPG | 0
docs/images/x60t_unbrick/0008.JPG | 0
docs/images/x60t_unbrick/0009.JPG | 0
docs/images/x60t_unbrick/0010.JPG | 0
docs/images/x60t_unbrick/0011.JPG | 0
docs/index.html | 240+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
docs/install/bbb_ehci.html | 514+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
docs/install/bbb_setup.html | 464+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
docs/install/c201.html | 320+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
docs/install/d510mo.html | 107+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
docs/install/ga-g41m-es2l.html | 129+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
docs/install/images/c201/battery-connector.jpg | 0
docs/install/images/c201/screws.jpg | 0
docs/install/images/c201/spi-flash-layout.jpg | 0
docs/install/images/c201/wp-screw.jpg | 0
docs/install/images/r400/0000.jpg | 0
docs/install/images/r400/0001.jpg | 0
docs/install/images/r400/0002.jpg | 0
docs/install/images/r400/0003.jpg | 0
docs/install/images/r400/0004.jpg | 0
docs/install/images/r400/0005.jpg | 0
docs/install/images/r400/0006.jpg | 0
docs/install/images/r400/0007.jpg | 0
docs/install/images/r400/0008.jpg | 0
docs/install/images/r400/0009.jpg | 0
docs/install/images/r400/0010.jpg | 0
docs/install/images/r400/0011.jpg | 0
docs/install/images/r400/0012.jpg | 0
docs/install/images/r400/0013.jpg | 0
docs/install/images/r400/0014.jpg | 0
docs/install/images/r400/0015.jpg | 0
docs/install/images/r400/0016.jpg | 0
docs/install/images/r400/0017.jpg | 0
docs/install/images/r400/0018.jpg | 0
docs/install/images/r400/0019.jpg | 0
docs/install/images/r400/0020.jpg | 0
docs/install/images/r400/0021.jpg | 0
docs/install/images/r400/0022.jpg | 0
docs/install/images/r400/0023.jpg | 0
docs/install/images/r400/0024.jpg | 0
docs/install/images/r400/0025.jpg | 0
docs/install/images/r400/0026.jpg | 0
docs/install/images/r400/0027.jpg | 0
docs/install/images/r400/0028.jpg | 0
docs/install/images/r400/0029.jpg | 0
docs/install/images/r400/0030.jpg | 0
docs/install/images/r400/0031.jpg | 0
docs/install/images/r400/0032.jpg | 0
docs/install/images/r400/0033.jpg | 0
docs/install/images/r400/0034.jpg | 0
docs/install/images/r400/0035.jpg | 0
docs/install/images/r400/0036.jpg | 0
docs/install/images/r400/0037.jpg | 0
docs/install/images/r400/0038.jpg | 0
docs/install/images/r400/0039.jpg | 0
docs/install/images/r400/0040.jpg | 0
docs/install/images/r400/0041.jpg | 0
docs/install/images/r400/0042.jpg | 0
docs/install/images/r400/0043.jpg | 0
docs/install/images/r400/0044.jpg | 0
docs/install/images/r400/0045.jpg | 0
docs/install/images/r400/0046.jpg | 0
docs/install/images/r400/0047.jpg | 0
docs/install/images/r400/0048.jpg | 0
docs/install/images/r400/0049.jpg | 0
docs/install/images/r400/0050.jpg | 0
docs/install/images/r400/0051.jpg | 0
docs/install/images/r400/0052.jpg | 0
docs/install/images/r400/r400_pomona.jpg | 0
docs/install/images/t400/0001.jpg | 0
docs/install/images/t400/0002.jpg | 0
docs/install/images/t400/0003.jpg | 0
docs/install/images/t400/0004.jpg | 0
docs/install/images/t400/0005.jpg | 0
docs/install/images/t400/0006.jpg | 0
docs/install/images/t400/0007.jpg | 0
docs/install/images/t400/0008.jpg | 0
docs/install/images/t400/0009.jpg | 0
docs/install/images/t400/0010.jpg | 0
docs/install/images/t400/0011.jpg | 0
docs/install/images/t400/0012.jpg | 0
docs/install/images/t400/0013.jpg | 0
docs/install/images/t400/0014.jpg | 0
docs/install/images/t400/0015.jpg | 0
docs/install/images/t400/0016.jpg | 0
docs/install/images/t400/0017.jpg | 0
docs/install/images/t400/0018.jpg | 0
docs/install/images/t400/0019.jpg | 0
docs/install/images/t400/0020.jpg | 0
docs/install/images/t400/0021.jpg | 0
docs/install/images/t400/0022.jpg | 0
docs/install/images/t400/0023.jpg | 0
docs/install/images/t400/0024.jpg | 0
docs/install/images/t400/0025.jpg | 0
docs/install/images/t400/0026.jpg | 0
docs/install/images/t400/0027.jpg | 0
docs/install/images/t400/0028.jpg | 0
docs/install/images/t400/0029.jpg | 0
docs/install/images/t400/0030.jpg | 0
docs/install/images/t400/0031.jpg | 0
docs/install/images/t400/0032.jpg | 0
docs/install/images/t400/0033.jpg | 0
docs/install/images/t400/0034.jpg | 0
docs/install/images/t400/0035.jpg | 0
docs/install/images/t400/0036.jpg | 0
docs/install/images/t400/0037.jpg | 0
docs/install/images/t400/0038.jpg | 0
docs/install/images/t400/0039.jpg | 0
docs/install/images/t400/0040.jpg | 0
docs/install/images/t400/0041.jpg | 0
docs/install/images/t400/0042.jpg | 0
docs/install/images/t400/0043.jpg | 0
docs/install/images/t400/0044.jpg | 0
docs/install/images/t400/0045.jpg | 0
docs/install/images/t400/0046.jpg | 0
docs/install/images/t400/0047.jpg | 0
docs/install/images/t400/0048.jpg | 0
docs/install/images/t400/0049.jpg | 0
docs/install/images/t400/0050.jpg | 0
docs/install/images/t400/0051.jpg | 0
docs/install/images/t400/0052.jpg | 0
docs/install/images/t400/0053.jpg | 0
docs/install/images/t400/0054.jpg | 0
docs/install/images/t400/0055.jpg | 0
docs/install/images/t400/0056.jpg | 0
docs/install/images/t400/0057.jpg | 0
docs/install/images/t400/0058.jpg | 0
docs/install/images/t400/0059.jpg | 0
docs/install/images/t400/0060.jpg | 0
docs/install/images/t400/0061.jpg | 0
docs/install/images/t400/0062.jpg | 0
docs/install/images/t400/0063.jpg | 0
docs/install/images/t400/0064.jpg | 0
docs/install/images/t400/0065.jpg | 0
docs/install/images/t400/0066.jpg | 0
docs/install/images/t400/0067.jpg | 0
docs/install/images/t400/0069.jpg | 0
docs/install/images/t400/0070.jpg | 0
docs/install/images/t400/0071.jpg | 0
docs/install/images/t400/0072.jpg | 0
docs/install/images/t400/ar5b95.jpg | 0
docs/install/images/t400/boot0.jpg | 0
docs/install/images/t400/boot1.jpg | 0
docs/install/images/t400/macaddress0.jpg | 0
docs/install/images/t400/macaddress1.jpg | 0
docs/install/images/t400/memory.jpg | 0
docs/install/images/t400/paste.jpg | 0
docs/install/images/t500/0000.jpg | 0
docs/install/images/t500/0001.jpg | 0
docs/install/images/t500/0002.jpg | 0
docs/install/images/t500/0003.jpg | 0
docs/install/images/t500/0004.jpg | 0
docs/install/images/t500/0005.jpg | 0
docs/install/images/t500/0006.jpg | 0
docs/install/images/t500/0007.jpg | 0
docs/install/images/t500/0008.jpg | 0
docs/install/images/t500/0009.jpg | 0
docs/install/images/t500/0010.jpg | 0
docs/install/images/t500/0011.jpg | 0
docs/install/images/t500/0012.jpg | 0
docs/install/images/t500/0013.jpg | 0
docs/install/images/t500/0014.jpg | 0
docs/install/images/t500/0015.jpg | 0
docs/install/images/t500/0016.jpg | 0
docs/install/images/t500/0017.jpg | 0
docs/install/images/t500/0018.jpg | 0
docs/install/images/t500/0019.jpg | 0
docs/install/images/t500/0020.jpg | 0
docs/install/images/t500/0021.jpg | 0
docs/install/images/t500/0022.jpg | 0
docs/install/images/t500/0023.jpg | 0
docs/install/images/t500/0024.jpg | 0
docs/install/images/t500/0025.jpg | 0
docs/install/images/t500/0026.jpg | 0
docs/install/images/t500/0027.jpg | 0
docs/install/images/t500/0028.jpg | 0
docs/install/images/t500/0029.jpg | 0
docs/install/images/t500/0030.jpg | 0
docs/install/images/t500/0031.jpg | 0
docs/install/images/t500/0032.jpg | 0
docs/install/images/t500/0033.jpg | 0
docs/install/images/t500/0034.jpg | 0
docs/install/images/t500/0035.jpg | 0
docs/install/images/t500/0036.jpg | 0
docs/install/images/t500/0037.jpg | 0
docs/install/images/t500/0038.jpg | 0
docs/install/images/t500/0039.jpg | 0
docs/install/images/t500/0040.jpg | 0
docs/install/images/t500/0041.jpg | 0
docs/install/images/t500/0042.jpg | 0
docs/install/images/t500/0043.jpg | 0
docs/install/images/t500/0044.jpg | 0
docs/install/images/t500/0045.jpg | 0
docs/install/images/t500/0046.jpg | 0
docs/install/images/t500/0047.jpg | 0
docs/install/images/t500/0048.jpg | 0
docs/install/images/t500/0049.jpg | 0
docs/install/images/t500/0050.jpg | 0
docs/install/images/t500/0051.jpg | 0
docs/install/images/t500/0052.jpg | 0
docs/install/images/t500/0053.jpg | 0
docs/install/images/t500/0054.jpg | 0
docs/install/images/t500/0055.jpg | 0
docs/install/images/t500/0056.jpg | 0
docs/install/images/t500/0057.jpg | 0
docs/install/images/t500/0058.jpg | 0
docs/install/images/t500/0059.jpg | 0
docs/install/images/t500/0060.jpg | 0
docs/install/images/t500/0061.jpg | 0
docs/install/images/t500/0062.jpg | 0
docs/install/images/x200/5252_bbb0.jpg | 0
docs/install/images/x200/5252_bbb1.jpg | 0
docs/install/images/x200/disassembly/0001.jpg | 0
docs/install/images/x200/disassembly/0002.jpg | 0
docs/install/images/x200/disassembly/0003.jpg | 0
docs/install/images/x200/disassembly/0004.jpg | 0
docs/install/images/x200/disassembly/0005.jpg | 0
docs/install/images/x200/disassembly/0006.jpg | 0
docs/install/images/x200/disassembly/0007.jpg | 0
docs/install/images/x200/disassembly/0008.jpg | 0
docs/install/images/x200/disassembly/0009.jpg | 0
docs/install/images/x200/disassembly/0010.jpg | 0
docs/install/images/x200/disassembly/0011.jpg | 0
docs/install/images/x200/disassembly/0012.jpg | 0
docs/install/images/x200/disassembly/0013.jpg | 0
docs/install/images/x200/disassembly/0014.jpg | 0
docs/install/images/x200/disassembly/0015.jpg | 0
docs/install/images/x200/disassembly/0016.jpg | 0
docs/install/images/x200/disassembly/0017.jpg | 0
docs/install/images/x200/disassembly/0018.jpg | 0
docs/install/images/x200/disassembly/0019.jpg | 0
docs/install/images/x200/ftdi.jpg | 0
docs/install/images/x200/ftdi_port.jpg | 0
docs/install/images/x200/psu33.jpg | 0
docs/install/images/x200/soic8.jpg | 0
docs/install/images/x200/wson_soldered.jpg | 0
docs/install/images/x200/x200_pomona.jpg | 0
docs/install/images/x60/th_bbb_flashing.jpg | 0
docs/install/index.html | 539+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
docs/install/kcma-d8.html | 109+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
docs/install/kgpe-d16.html | 124+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
docs/install/r400_external.html | 596+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
docs/install/t400_external.html | 579+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
docs/install/t500_external.html | 589+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
docs/install/t60_unbrick.html | 322+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
docs/install/x200_external.html | 477+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
docs/install/x60_unbrick.html | 318+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
docs/install/x60flashscript.patch | 27+++++++++++++++++++++++++++
docs/install/x60tablet_unbrick.html | 215+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
docs/maintain/index.html | 656+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
docs/misc/index.html | 328+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
docs/misc/patch.html | 218+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
docs/release.html | 290+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
docs/security/dock.html | 190+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
docs/security/index.html | 76++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
docs/security/t60_security.html | 484+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
docs/security/x60_security.html | 344+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
docs/t7200q/.htaccess | 2++
docs/t7200q/cbmemc | 1448+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
docs/t7200q/kernel | 1016+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
docs/t7200q/t7200_01.jpg | 0
docs/t7200q/t7200_02.jpg | 0
568 files changed, 71319 insertions(+), 0 deletions(-)

diff --git a/docs/archive_old.html b/docs/archive_old.html @@ -0,0 +1,1531 @@ +<!DOCTYPE html> +<html> +<head> + <meta charset="utf-8"> + <meta name="viewport" content="width=device-width, initial-scale=1"> + + <style type="text/css"> + @import url('css/main.css'); + </style> + + <title>Libreboot release information (old)</title> +</head> +<body> + + <div class="section"> + + <h1 id="pagetop">Libreboot release information (old)</h1> + <p> + Information for this release can be found at <a href="release.html">release.html</a>. + Updated versions of libreboot can be found at <a href="http://libreboot.org/">libreboot.org</a>. + </p> + + <div class="important"> + <p> + <b>This page is *obsolete*, provided for historical purposes.</b> + </p> + </div> + + </div> + + <div class="section"> + + <h2>Releases</h2> + <ul> + <li><a href="#release20150518">r20150518 (18th May 2015)</a></li> + <li><a href="#release20150124">r20150124 (24th January 2015), r20150126 (26th January 2015), r20150208 (8th February 2015)</a></li> + <li><a href="#release20141015">r20141015 (15th October 2014)</a></li> + <li><a href="#release20140911">r20140911 (6th release)</a> (11th September 2014 <b>pre-release, 7th beta</b>)</li> + <li><a href="#release20140622">r20140622 (5th release)</a> (7th March 2014, revised 22nd June 2014)</li> + <li><a href="#release20140221">r20140221 (4th release)</a> (21st February 2014)</li> + <li><a href="#release20131214">r20131214 (3rd release)</a> (14th December 2013)</li> + <li><a href="#release20131213">r20131213 (2nd release)</a> (13th December 2013)</li> + <li><a href="#release20131212">r20131212 (1st release)</a> (12th December 2013)</li> + </ul> + + </div> + + <div class="section"> + + <h1 id="release20150518">Release 20150518</h1> + + <p> + Release date: 18th May 2015. + </p> + + <p> + Installation instructions can be found at <b><i>docs/install/index.html</i></b>. + Building instructions (for source code) can be found at <b><i>docs/git/index.html#build</i></b>. + </p> + + <h2>Machines supported in this release:</h2> + <ul> + <li> + <b>ThinkPad X60/X60s</b> + <ul> + <li> + You can also remove the motherboard from an X61/X61s and replace it with an X60/X60s motherboard. + An X60 Tablet motherboard will also fit inside an X60/X60s. + </li> + </ul> + </li> + <li> + <b>ThinkPad X60 Tablet</b> (1024x768 and 1400x1050) with digitizer support + <ul> + <li>See <b><i>docs/hcl/index.html#supported_x60t_list</i></b> for list of supported LCD panels</li> + <li>It is unknown whether an X61 Tablet can have it's mainboard replaced with an X60 Tablet motherboard.</li> + </ul> + </li> + <li> + <b>ThinkPad T60</b> (Intel GPU) (there are issues; see below): + <ul> + <li>See notes below for exceptions, and <b><i>docs/hcl/index.html#supported_t60_list</i></b> for known working LCD panels.</li> + <li>It is unknown whether a T61 can have it's mainboard replaced with a T60 motherboard.</li> + <li>See <b><i>docs/future/index.html#t60_cpu_microcode</i></b>.</li> + <li>T60P (and T60 laptops with ATI GPU) will likely never be supported: <b><i>docs/hcl/index.html#t60_ati_intel</i></b></li> + </ul> + </li> + <li> + <b>ThinkPad X200</b> + <ul> + <li>X200S and X200 Tablet are also supported, conditionally; see <b><i>docs/hcl/x200.html#x200s</i></b></li> + <li><b>ME/AMT</b>: libreboot removes this, permanently. <b><i>docs/hcl/gm45_remove_me.html</i></b></li> + </ul> + </li> + <li> + <b>ThinkPad R400</b> + <ul> + <li>See <b><i>docs/hcl/r400.html</i></b></li> + <li><b>ME/AMT</b>: libreboot removes this, permanently. <b><i>docs/hcl/gm45_remove_me.html</i></b></li> + </ul> + </li> + <li> + <b>ThinkPad T400</b> + <ul> + <li>See <b><i>docs/hcl/t400.html</i></b></li> + <li><b>ME/AMT</b>: libreboot removes this, permanently. <b><i>docs/hcl/gm45_remove_me.html</i></b></li> + </ul> + </li> + <li> + <b>ThinkPad T500</b> + <ul> + <li>See <b><i>docs/hcl/t500.html</i></b></li> + <li><b>ME/AMT</b>: libreboot removes this, permanently. <b><i>docs/hcl/gm45_remove_me.html</i></b></li> + </ul> + </li> + <li> + <b>Apple MacBook1,1</b> (MA255LL/A, MA254LL/A, MA472LL/A) + <ul> + <li>See <b><i>docs/hcl/index.html#macbook11</i></b>.</li> + </ul> + </li> + <li> + <b>Apple MacBook2,1</b> (MA699LL/A, MA701LL/A, MB061LL/A, MA700LL/A, MB063LL/A, MB062LL/A) + <ul> + <li>See <b><i>docs/hcl/index.html#macbook21</i></b>.</li> + </ul> + </li> + </ul> + + <h2> + Changes for this release, relative to r20150208 (earliest changes last, recent changes first) + </h2> + <ul> + <li>Add a whitelist entry to board_enable.c in flashrom, for the ThinkPad R400, T400 and T500</li> + <li> + Updated flashrom (to SVN revision 1889) + <ul> + <li>X200 whitelist patch removed (merged upstream)</li> + <li>X200 whitelist modified to include X200S and X200 Tablet</li> + </ul> + </li> + <li>libreboot_util: don't include cmos layout files (not needed anymore)</li> + <li><b>coreboot-libre: backport patches for X200 Tablet digitizer support</b></li> + <li>build/release/archives: create SHA512 sum manifest file of the release archives</li> + <li>build/release/archives: separate crossgcc into a new archive</li> + <li>disabled generation of txtmode ROM images for now (they will be back again in the next release)</li> + <li>coreboot-libre: delete unused code (reduce size of src archive)</li> + <li>Flashing guides: make them more friendly to colourblind people</li> + <li> + docs/gnulinux/encrypted_*.html: Remove mention of password length + - it was arbitrary and pointless. + </li> + <li>docs/maintain/index.html: Finish the guide</li> + <li> + scripts/download/coreboot: use diffs included in libreboot, not external gerrit cherry-picks + - review.coreboot.org (gerrit) being down no longer kills + libreboot (backup mirrors of the master repository exist) + </li> + <li>docs/install/bbb_setup.html: Add info about wp/hold and pinouts</li> + <li>docs/index.html: improve the description of libreboot</li> + <li>docs/hcl/gm45_remove_me.html: notes about the demefactory utility</li> + <li>docs/install/bbb_setup.html: EHCI debug: recommend linux-libre</li> + <li>docs/install/bbb_setup.html: EHCI Debug logging setup guide</li> + <li>docs/hcl/t500.html: Add screen compatibility report (TODO: fix incompatible screens)</li> + <li> + Update coreboot(again) + merge GM45 hybrid GPU patches + - means that T400/T500 with the ATI+Intel hybrid GPU setup + will work (ATI disabled, Intel permanently enabled). + power_on_after_fail nvram option added to all GM45 boards, + defaulting to No, so that plugging it AC doesn't boot up + the system against the users will. Net20DC is now the default + debug dongle on all boards (compatible with BBB). + </li> + <li>demefactory (new utility): create GM45 factory.rom without the ME</li> + <li>ich9deblob: re-factor descriptor.c functions</li> + <li>docs/hcl/t500.html: add hardware logs</li> + <li>docs/gnulinux/encrypted_*.html: No password for default entry</li> + <li>docs/git/index.html: Add more details about BUC.TS</li> + <li>grub.cfg: Also scan for grub2/grub.cfg, not just grub/grub.cfg</li> + <li>docs/maintain/ (new section. WIP!): Maintaining libreboot</li> + <li>docs/gnulinux/grub_boot_installer.html: Fix hazardous instruction</li> + <li>docs/tasks.html: Better categorization between intel/amd/arm</li> + <li>docs/install/bbb_setup.html: notes about SPI flashing stability</li> + <li>docs/install/bbb_setup.html: more names for the 0.1&quot; cables</li> + <li>docs/install/*_external.html: add disclaimer about thermal paste</li> + <li>docs/install/bbb_setup.html: Fix broken links</li> + <li>docs/install/bbb_setup.html: preliminary notes about EHCI debug</li> + <li>docs/hcl/gm45_remove_me.html: Link to websites talking about the ME</li> + <li>docs/install/{t400,t500,r400}_external.html: Notes about CPU compatibility</li> + <li>Delete the ich9macchange script. It's useless, and confuses people</li> + <li>docs/hcl/gm45_remove_me.html: prioritize ich9gen executable path</li> + <li>docs/hcl/gm45_remove_me.html: prioritize changing mac address</li> + <li>docs/hcl/gm45_remove_me.html: less confusing notes about ich9gen</li> + <li>build/dependencies/parabola: Add dependencies for x86_64</li> + <li>Move parabola/trisquel dependency scripts to scripts/helpers/build</li> + <li>scripts/dependencies/paraboladependencies: build dependencies (32-bit Parabola)</li> + <li><b>New board</b>: ThinkPad T500</li> + <li>Add diffs for descriptor/gbe differences between T500 and X200</li> + <li>coreboot-libre: provide better blob categorization</li> + <li>docs/hcl/gm45_remove_me.html: add notes about flash write protect</li> + <li><b>New board</b>: ThinkPad T400</li> + <li>GRUB: add partial vesamenu.c32 support (fixes tails ISOLINUX menu)</li> + <li>Update GRUB (to revision fa07d919d1ff868b18d8a42276d094b63a58e299)</li> + <li> + Update coreboot (to revision 83b05eb0a85d7b7ac0837cece67afabbdb46ea65) + <ul> + <li> + Intel CPU microcode (most of it) no longer deleted, + because it was deleted upstream (moved to a 3rd + party repository). + </li> + <li>MacBook2,1 cstate patch is no longer cherry picked (merged upstream)</li> + <li>Patch to disable use of timestamps in coreboot no longer included (merged upstream)</li> + </ul> + </li> + <li>coreboot-libre: don't list vortex86ex kbd firmware as microcode (list it separately)</li> + <li>coreboot-libre: don't rm */early_setup_ss.h (these are not blobs)</li> + <li>coreboot-libre: add GPLv3 license to the findblobs script</li> + <li>coreboot-libreboot: don't rm raminit_tables (nahelem/sandybridge) (they are not blobs)</li> + <li>coreboot-libre: don't delete the .spd.hex files (they are not blobs)</li> + <li>build/release/archives: don't put rmodtool in libreboot_util</li> + <li>docs/install/x200_external.html: recommend installing GNU/Linux at the end</li> + <li>docs/install/x200_external.html: add more photos, improve instructions</li> + <li>build/clean/grub: use distclean instead of clean</li> + <li>grub-assemble: Add the <i>bsd</i> and <i>part_bsd</i> modules</li> + <li>build/roms/withgrub: Only run ich9gen if gm45/gs45 images exist</li> + <li>docs/git/index.html: Add notes about building for specific boards</li> + <li>build/roms/withgrub: Allow building for a custom range of boards</li> + <li>grub-assemble: Disable verbose output</li> + <li>Add documentation on how to unlock root encrypted fs with key in initramfs in Parabola Linux</li> + <li>docs/gnulinux/grub_cbfs.html: Improve structure (easier to use)</li> + <li>grub.cfg: Disable the beep on startup</li> + <li>docs/install/bbb_setup.html: Make the guide easier to use</li> + <li>docs/gnulinux/grub_cbfs.html: Remove redundant instructions</li> + <li>docs/install/x200_external.html: Mark pins in the images</li> + <li>docs/install/bbb_setup.html: Replace 3.3V PSU photo with ATX PSU</li> + <li>docs/hcl/x200.html: Add dumps from 4-MiB X200 with Lenovo BIOS 3.22</li> + <li>docs/hcl/x200.html: Add dumps from 4-MiB X200 with Lenovo BIOS 3.18</li> + <li>grub.cfg: add syslinux_configfile menuentry for ahci0</li> + <li>grub.cfg: Add more paths for syslinux_configfile</li> + <li>docs/future.html: T60: Add EDID dump from LG-Philips LP150E05-A2K1</li> + <li>docs/install/bbb_setup.html: Further clarify which clip is needed</li> + <li>bash scripts: Make script output more user-friendly in general</li> + <li>bash scripts: Only enable verbose output if DEBUG= is used</li> + <li> + build: Support multiple extra options + - now possible to build multiple images for arbitrary + boards (configs), but without building the entire + collection. + </li> + <li> + Deleted the signing archive key + - the finger print and ID is given instead, so that + the user can download it from a key server + </li> + <li> + scripts/helpers/build/release: Move docs to separate archive + - reduces the size of the other archives considerably + </li> + <li>Move DEBLOB to resources/utilities/coreboot-libre/deblob</li> + <li> + scripts/helpers/build/release: Delete DEBLOB from libreboot_src/ + - not needed in libreboot_src (release archive) because it + contains a coreboot revision that has already been deblobbed. + </li> + <li>flash (script): Use <i>build</i> instead of <i>DEBLOB</i> to know if in src</li> + <li>docs/install/r400_external.html: Show images, don't link.</li> + <li>docs/install/x200_external.html: Show images, don't link.</li> + <li>docs/install/bbb_setup.html: Show images, instead of linking</li> + <li>Documentation: optimize all images (reduce file sizes)</li> + <li> + Remove download links from the release page (and the archive page) + - release archives are hosted differently following this release, + which means that the old methods are no longer viable. + </li> + <li>Moved ich9macchange to resources/scripts/misc/ich9macchange</li> + <li> + ich9macchange: assume that the script is being run from _util + (act only on one ROM image, defined by a user-provided path) + </li> + <li>Move grub-background to resources/scripts/misc/grub-background</li> + <li>grub-background: assume that it is being run from libreboot_util</li> + <li>grub-background: change only one ROM image, specified by path</li> + <li>build (release archives): Add the commitid file to release/</li> + <li>build-release: Move the release archives to release/</li> + <li> + Merge all build scripts into a single generic script, + with helpers in resources/scripts/helpers/build/ + </li> + <li> + Replace <i>getall</i> with <i>download</i>, which takes as input an argument + specifying which program the user wants to download. + </li> + <li>Moved the get scripts to resources/scripts/helpers/download/</li> + <li>build-release: Remove the powertop entries</li> + <li>Moved powertop.trisquel7 to resources/scripts/misc/</li> + <li>Deleted the powertop.trisquel6 script (Trisquel 6 is obsolete)</li> + <li>Documentation: general improvements to the flashing instructions</li> + <li>Merged all flashing scripts into a single script</li> + <li>Updated GRUB</li> + <li>bucts: Make it build without git</li> + <li>Moved dejavu-fonts-ttf-2.34/AUTHORS to resources/grub/font/</li> + <li>Deleted GRUB Invaders from libreboot</li> + <li>Deleted SeaBIOS from libreboot</li> + <li>build-release: optimize use of tar (reduced file sizes)</li> + <li>grub.cfg: add another SYSLINUX config location (/syslinux/syslinux.cfg)</li> + <li>build-release: remove the bin/ directory from libreboot_util</li> + <li>cleandeps: delete the bin/ directory</li> + <li>buildrom-withgrub: create the bin directory if it does not exist</li> + <li>coreboot-libre: don't use git for version timestamp</li> + <li>i945-pwm: add clean command to Makefile</li> + <li>i945-pwm: add -lz to Makefile</li> + <li>docs/install/x200_external: Mention GPIO33 non-descriptor mode</li> + <li>docs/hcl/index.html: Remove redundant links</li> + <li>ich9macchange: Add R400</li> + <li>build-release: Separate ROM images into individual archives</li> + <li>build-release: rename libreboot_bin to libreboot_util</li> + <li><b>New board:</b> ThinkPad R400 support added to libreboot.</li> + <li>bbb_setup.html: tell user to use libreboot's own flashrom</li> + </ul> + + </div> + + <div class="section"> + + <h1 id="release20150124">Release 20150124, 20150126 and 20150208</h1> + + <p> + Release date: 24th January 2015. + </p> + + <h2>Machines supported in this release:</h2> + <ul> + <li> + <b>Lenovo ThinkPad X60/X60s</b> + <ul> + <li> + You can also remove the motherboard from an X61/X61s and replace it with an X60/X60s motherboard. + An X60 Tablet motherboard will also fit inside an X60/X60s. + </li> + </ul> + </li> + <li> + <b>Lenovo ThinkPad X60 Tablet</b> (1024x768 and 1400x1050) with digitizer support + <ul> + <li>See <b>hcl/index.html#supported_x60t_list</b> for list of supported LCD panels</li> + <li>It is unknown whether an X61 Tablet can have it's mainboard replaced with an X60 Tablet motherboard.</li> + </ul> + </li> + <li> + <b>Lenovo ThinkPad T60</b> (Intel GPU) (there are issuesinstall/x200_external.html; see below): + <ul> + <li>See notes below for exceptions, and <b>hcl/index.html#supported_t60_list</b> for known working LCD panels.</li> + <li>It is unknown whether a T61 can have it's mainboard replaced with a T60 motherboard.</li> + <li>See <b>future/index.html#t60_cpu_microcode</b>.</li> + <li>T60P (and T60 laptops with ATI GPU) will likely never be supported: <b>hcl/index.html#t60_ati_intel</b></li> + </ul> + </li> + <li> + <b>Lenovo ThinkPad X200</b> + <ul> + <li>X200S and X200 Tablet are also supported, conditionally; see <b>hcl/x200.html#x200s</b></li> + <li><b>ME/AMT</b>: libreboot removes this, permanently. <b>hcl/gm45_remove_me.html</b></li> + </ul> + </li> + <li> + <b>Lenovo ThinkPad R400</b> (r20150208 and later, only) + <ul> + <li><b>ME/AMT</b>: libreboot removes this, permanently. <b>hcl/gm45_remove_me.html</b></li> + </ul> + </li> + <li> + <b>Apple MacBook1,1</b> (MA255LL/A, MA254LL/A, MA472LL/A) + <ul> + <li>See <b>hcl/index.html#macbook11</b>.</li> + </ul> + </li> + <li> + <b>Apple MacBook2,1</b> (MA699LL/A, MA701LL/A, MB061LL/A, MA700LL/A, MB063LL/A, MB062LL/A) + <ul> + <li>See <b>hcl/index.html#macbook21</b>.</li> + </ul> + </li> + </ul> + + <h2> + Revisions for r20150208 (relative to r20150126) + </h2> + <p> + This is a maintenance release (polishing) based on r20150126. Users who installed r20150126 + don't really need to update to this release. + </p> + <ul> + <li>buildrom-withgrub: use gnulove.jpg background on 16:10 laptops (MacBook2,1 and X200)</li> + <li>build-release: include grub-background script in libreboot_bin</li> + <li>grub-background (new): lets user change GRUB background image</li> + <li>grub-assemble: Add link to original utility.</li> + <li>buildrom-withgrub: Put background.jpg in CBFS, not GRUB memdisk</li> + <li>grub-assemble: merge scripts into a single script gen.sh</li> + <li>Documentation: implement theme, drastically improve readability</li> + <li>docs/hcl/index.html: update list of compatible T60 LCD panels</li> + <li>docs/index.html: more clarification of libreboot's stated purpose.</li> + <li>build-release: include the commitid file in the release archives</li> + <li>docs/index.html: Further emphasize the GNU/Linux requirement.</li> + <li>lenovobios_firstflash: fix BASH errors</li> + <li>lenovobios_secondflash: fix BASH errors</li> + <li>docs/install/x200_external.html: Tell user to switch MAC address.</li> + <li>docs/git/index.html: Add to the list of x86_64 compatible hosts.</li> + <li>docs/install/index.html: Remove old (obsolete) information.</li> + <li>docs/git/index.html: Say that the build dependencies are for src (and not nedeed for libreboot_bin)</li> + <li>build: re-factor the descriptor/gbe generating loop for GM45/ICH9M</li> + <li>X60, X60S and X60 Tablet now the same ROM images.</li> + <li>Add QEMU (q35/ich9) support to libreboot.</li> + <li>Add QEMU (i440fx/piix4) support to libreboot</li> + <li>docs/index.html: Re-write the description of what libreboot is.</li> + <li>docs/release.html: Add notes about how to use GPG.</li> + <li>build-release: delete the commitid file from release archives</li> + <li>build-release: create file named commitid after build-release</li> + </ul> + <h2> + Revisions for r20150126 (relative to r20150124) + </h2> + <p> + This is a bug fix release based on r20150124. It contains a few small changes: + </p> + <ul> + <li>grub.cfg: hardcode the list of partitions to search (speeds up booting considerably. GRUB regexp isn't very well optimized)</li> + <li>Docs (x200.html hcl): Remove incorrect information</li> + <li>Documentation (bbb_setup.html): Fix typos</li> + <li> + build-release: delete ich9fdgbe_{4m,8m}.bin files from ich9gen + <ul> + <li> + These were accidentically included in the r20150124 release. They + are generated from ich9gen so it's ok, but they don't need to be + in the archive. + </li> + </ul> + </li> + <li>Documentation (grub_cbfs.html): Looping in libreboot_grub.cfg (Add notes about it if the user copied from grub.cfg in CBFS.)</li> + <li>Documentation: refer to Guix as GNU Guix System Distribution or GNU GSD per advice from the Guix project.</li> + </ul> + <h2> + Changes for this release (latest changes first, earliest changes last) + </h2> + <ul> + <li>Documentation: added information about how to boot Guix GNU/Linux.</li> + <li>grub.cfg: Added (usb0) and (usb0,*) to the list of devices in the <i>Search for GRUB</i> menuentry (this is needed for Guix GNU/Linux)</li> + <li>grub.cfg: Added (ahci1) to list of devices for ISOLINUX parser (CD/DVD) (this is needed for the X200 docking station).</li> + <li>grub.cfg: ISOLINUX parsing is now done on all USB partitions.</li> + <li>grub.cfg: Automatically switched to /boot/grub/libreboot_grub.cfg on a partition, if it exists.</li> + <li>libreboot_bin: added static ARM binaries for flashrom, cbfstool, ich9gen and + ich9deblob (tested on beaglebone black).</li> + <li>Flashrom: removed redundant Macronix flashchip definitions (for X200 owners).</li> + <li>Flashrom: added whitelist for ThinkPad X200.</li> + <li>X200: fixed uneven backlight (at low levels)</li> + <li>ich9macchange (new script, uses ich9gen): for changing the default MAC address on X200 ROM images.</li> + <li>ich9gen: added capability to change the default MAC address (and update the checksum)</li> + <li>ich9deblob: added new utility ich9gen: this can generate a descriptor+gbe image without a factory.rom dump present.</li> + <li>Modified ich9deblob to use a struct for Gbe, documenting everything.</li> + <li>Massively updated the ich9deblob utility: re-factored everything completely.</li> + <li>Enabled cstates 1 and 2 on macbook21. This reduces idle heat / power consumption.</li> + <li>buildrom-withgrub: disabled creation of *txtmode*.rom for X200 (only framebuffer graphics work)</li> + <li>Updated SeaBIOS (again)</li> + <li>docs/install/index.html#flashrom_x200: improve instructions</li> + <li>Updated flashrom (again) - patches updated</li> + <li>Updated GRUB (again)</li> + <li>Updated coreboot (again)</li> + <li>build-release: not all files were copied to libreboot_src. fix that.</li> + <li>build-release: include cbmem (statically compiled) in libreboot_bin</li> + <li>Documentation (X200): added software-based flashing instructions</li> + <li>Documentation: remove all references to the bus pirate (replaced with BBB flashing tutorials)</li> + <li><b>New board:</b> ThinkPad X200S and X200 Tablet support added to libreboot</li> + <li>build: automatically find board names (configs) to build for</li> + <li><b>New board:</b> ThinkPad X200 support added to libreboot</li> + <li>coreboot-libre config (all boards): enable USB dongle log output (for BeagleBone Black)</li> + <li>cleandeps: actually clean grubinvaders</li> + <li>.gitignore: add powertop directory</li> + <li>cleandeps: clean i945-pwm utility</li> + <li>scripts (all): fix typos</li> + <li>Documentation: general cleanup.</li> + <li>builddeps-flashrom: reduce build commands to a single for loop</li> + <li>scripts (all): replace unnecessary rm -Rf with rm -f</li> + <li>powertop.trisquel7: remove sudo (script already checks if the user is root)</li> + <li>docs/release.html: add lenovo g505s to the list of candidates</li> + <li>.gitignore: add libreboot_bin.tar.xz and libreboot_src.tar.xz</li> + <li> + libreboot_bin.tar.xz: Include utils as statically linked binaries + <ul> + <li>This means that the user does not have to install build dependency + or build from source anymore.</li> + </ul> + </li> + <li>deps-trisquel: Add binutils-source</li> + <li>powertop.trisquel7 (new): Setup powertop on trisquel 7</li> + <li>deps-trisquel,flash,lenovobios_firstflash,lenovobios_secondflash,macbook21_firstflash + x60flashfrom5,powertop.trisquel6: check if user is root</li> + <li>deps-trisquel: Make GRUB build on in Trisquel 7 x86_64. (cross compile dependencies. fixes build error in GRUB)</li> + <li>deps-parabola (removed) Remove Parabola dependencies script. Will re-add later (properly tested)</li> + <li>grub.cfg: Add more path checks to isolinux parser (more ISOs should work now)</li> + <li>Update SeaBIOS</li> + <li>x60flashfrom5 (new), for X60 users upgrading from 5th/early release</li> + <li>Update flashrom</li> + <li>Update GRUB</li> + <li> + Updated coreboot-libre + <ul> + <li>i945: permanently set tft_brightness to 0xff (fixes bug on X60 where + turning up brightness at max would make it loop back to low brightness)</li> + </ul> + </li> + <li> + getcb: Revert X60/T60 to legacy backlight controls + <ul> + <li>The ACPI brightness patches were abandoned and obsolete.</li> + </ul> + </li> + <li>grub.cfg: Only load initrd.img if it exists. Add rw to linux line (for ProteanOS)</li> + <li>build: Only generate the GRUB configurations once (re-use on all images)</li> + <li>Only build 2 GRUB payload executables, re-use on all boards.</li> + <li> + resources/utilities/grub-assemble/gen.txtmode.sh: Use GNU BASH<br/> + resources/utilities/grub-assemble/gen.vesafb.sh: Use GNU BASH + </li> + <li>scripts (error handling): Replace exit with exit 1 (make debugging easier)</li> + <li> + Move most files in CBFS to GRUB memdisk, except grub.cfg and grubtest.cfg + <ul> + This reduces the space used in CBFS because coreboot compresses + its payloads with LZMA by default. grub.cfg is all that most users + will want to modify, which remains in CBFS. + </ul> + </li> + <li>docs/release.html Add DMP vortex86ex to list of candidates.</li> + <li>docs/release.html Add ThinkPad X201 to list of candidates.</li> + <li>New links added to docs/security/x60_security and docs/security/t60_security</li> + <li>lenovobios_secondflash: Warn if BUCTS is not present. (not a dealbreaker. Can just pull out nvram battery/coin).</li> + <li>lenovobios_firstflash: Fail if BUCTS fails. (anti-bricking precaution)</li> + <li>Removed obnoxious warnings from flashing scripts, improved documentation instead.</li> + <li>scripts (all): add proper error checking (fail fast, fail early. Do not continue if there are errors)</li> + <li>buildrom-withgrub: rename image to boardname_layout_romtype.rom</li> + <li>buildrom-withgrub: don't move cbfstool, execute directly</li> + <li>resources/utilities/grub-assemble: add French Dvorak (BEPO) keyboard layout.</li> + <li>Documentation: add docs/hardware/x60_keyboard.html (show how to replace keyboard on X60/X60T)</li> + <li>Documentation: major cleanup (better structure, easier to find things)</li> + <li> + docs/release.html: Remove Acer CB5 from list of future candidates. + <ul> + <li> + Too many issues. Chromebooks are crippled (soldered RAM/storage/wifi) + and have too many usability issues for the libreboot project. + </li> + </ul> + </li> + <li>docs/gnulinux/grub_cbfs.html Major cleanup. Usability improvements.</li> + <li>hocs/gnulinux/encrypted_trisquel.html: Fixed mistakes/typos. General improvements</li> + <li> + flash (flashrom script): remove boardmismatch=force + <ul> + <li> + This was put there before for users upgrading from libreboot r5 + to r6, but also allows the user to flash the wrong image. For + example, the user could flash a T60 image on an X60, thus + bricking the system. It's almost certain that most people + have upgraded by now, so remove this potentially dangerous + option. + </li> + </ul> + </li> + <li>Documentation: update compatibility list for X60T LCD panels.</li> + <li>docs/release.html: add note about X60 Tablet board in X60/X60s</li> + <li>docs/howtos/grub_boot_installer.html: small corrections</li> + <li>docs/howtos/grub_boot_installer.html: improved readability, fixed html errors</li> + <li>Documentation (macbook21 related): clean up</li> + </ul> + + </div> + + <div class="section"> + + <h1 id="release20141015">Release 20141015</h1> + + <h2>Machines supported in this release:</h2> + <ul> + <li> + <b>Lenovo ThinkPad X60/X60s</b> + <ul> + <li> + You can also remove the motherboard from an X61/X61s and replace it with an X60/X60s motherboard. + An X60 Tablet motherboard will also fit inside an X60/X60s. + </li> + </ul> + </li> + <li> + <b>Lenovo ThinkPad X60 Tablet</b> (1024x768 and 1400x1050) with digitizer support + <ul> + <li>See <b>hcl/index.html#supported_x60t_list</b> for list of supported LCD panels</li> + <li>It is unknown whether an X61 Tablet can have its mainboard replaced with an X60 Tablet motherboard.</li> + </ul> + </li> + <li> + <b>Lenovo ThinkPad T60</b> (Intel GPU) (there are issues; see below): + <ul> + <li>See notes below for exceptions, and <b>hcl/index.html#supported_t60_list</b> for known working LCD panels.</li> + <li>It is unknown whether a T61 can have its mainboard replaced with a T60 motherboard.</li> + <li>See <b>future/index.html#t60_cpu_microcode</b>.</li> + <li>T60P (and T60s with ATI GPU) will likely never be supported: <b>hcl/index.html#t60_ati_intel</b></li> + </ul> + </li> + <li> + <b>Apple MacBook1,1</b> (MA255LL/A, MA254LL/A, MA472LL/A) + <ul> + <li>See <b>hcl/index.html#macbook11</b>.</li> + </ul> + </li> + <li> + <b>Apple MacBook2,1</b> (MA699LL/A, MA701LL/A, MB061LL/A, MA700LL/A, MB063LL/A, MB062LL/A) + <ul> + <li>See <b>hcl/index.html#macbook21</b>.</li> + </ul> + </li> + </ul> + + <h2> + Changes for this release (latest changes first, earliest changes last) + </h2> + <ul> + <li>Updated coreboot (git commit 8ffc085e1affaabbe3dca8ac6a89346b71dfc02e), the latest at the time of writing.</li> + <li>Updated SeaBIOS (git commit 67d1fbef0f630e1e823f137d1bae7fa5790bcf4e), the latest at the time of writing.</li> + <li>Updated Flashrom (svn revision 1850), the latest at the time of writing.</li> + <li>Updated GRUB (git commit 9a67e1ac8e92cd0b7521c75a734fcaf2e58523ad), the latest at the time of writing.</li> + <li>Cleaned up the documentation, removed unneeded files.</li> + <li>ec/lenovo/h8 (x60/x60s/x60t/t60): Enable wifi/bluetooth/wwan/touchpad/trackpoint by default.</li> + <li>Documentation: Updated list of T60 LCDs (Samsung LTN150XG 15&quot; XGA listed as non-working).</li> + <li>builddeps-coreboot: Don't build libpayload (not needed. This was leftover by mistake, when trying out the TINT payload).</li> + <li>Replaced most diff files (patches) for coreboot with gerrit checkouts (cherry-pick).</li> + <li>Documentation: x60_security.html and t60_security.html: added links to info about the ethernet controller (Intel 82573).</li> + <li>Documentation: x60_security.html and t60_security.html: added notes about DMA and the docking station.</li> + <li> + Documentation: configuring_parabola.html: basic post-install steps for Parabola GNU/Linux + (helpful, since libreboot development is being moved to Parabola at the time of writing). + </li> + <li>builddeps-coreboot: use 'make crossgcc-i386' instead of 'make crossgcc'. Libreboot only targets x86 at the time of writing.</li> + <li>ROM images no longer include SeaBIOS. Instead, the user adds it afterwards. Documentation and scripts updated.</li> + <li>docs/images/encrypted_parabola.html: Notes about linux-libre-grsec</li> + <li>Documentation: encrypted_parabola.html: add tutorial for encrypted Parabola GNU/Linux installation.</li> + <li>Documentation: added more info about wifi chipsets</li> + </ul> + + <p><a href="#pagetop">Back to top of page.</a></p> + + </div> + + <div class="section"> + + <h1 id="release20140911">6th release (pre-release, 7th beta)</h1> + + <ul> + <li>Released 11th July 2014 (pre-release) 1st beta</li> + <li>Revised (pre-release, 2nd beta) 16th July 2014</li> + <li>Revised (pre-release, 3rd beta) 20th July 2014</li> + <li>Revised (pre-release, 4th beta) 29th July 2014</li> + <li>Revised (pre-release, 5th beta) 11th August 2014 (corrected 11th August 2014)</li> + <li>Revised (pre-release, 6th beta) 3rd September 2014</li> + <li>Revised (pre-release, 7th beta) 11th September 2014</li> + </ul> + + <h2>Machines still supported (compared to previous release):</h2> + <ul> + <li> + <b>Lenovo ThinkPad X60/X60s</b> + <ul> + <li> + You can also remove the motherboard from an X61/X61s and replace it with an X60/X60s motherboard. + </li> + </ul> + </li> + </ul> + <h2>New systems supported in this release:</h2> + <ul> + <li> + <b>Lenovo ThinkPad X60 Tablet</b> (1024x768 and 1400x1050) with digitizer support + <ul> + <li>See <b>hcl/index.html#supported_x60t_list</b> for list of supported LCD panels</li> + <li>It is unknown whether an X61 Tablet can have its mainboard replaced with an X60 Tablet motherboard.</li> + </ul> + </li> + <li> + <b>Lenovo ThinkPad T60</b> (Intel GPU) (there are issues; see below) + <ul> + <li>See notes below for exceptions, and <b>hcl/index.html#supported_t60_list</b> for known working LCD panels.</li> + <li>It is unknown whether a T61 can have its mainboard replaced with a T60 motherboard.</li> + <li>T60P (and T60s with ATI GPU) will likely never be supported: <b>hcl/index.html#t60_ati_intel</b></li> + </ul> + </li> + <li> + <b>Apple MacBook1,1</b> (MA255LL/A, MA254LL/A, MA472LL/A) + <ul> + <li>See <b>hcl/index.html#macbook11</b>.</li> + </ul> + </li> + <li> + <b>Apple MacBook2,1</b> (MA699LL/A, MA701LL/A, MB061LL/A, MA700LL/A, MB063LL/A, MB062LL/A) + <ul> + <li>See <b>hcl/index.html#macbook21</b>.</li> + </ul> + </li> + </ul> + <h2>Machines no longer supported (compared to previous release):</h2> + <ul> + <li><b>All previous systems still supported!</b></li> + </ul> + + <h2> + Revisions for r20140911 (7th beta) (11th September 2014) + </h2> + <ul> + <li>The changes below were made in a git repository, unlike in previous releases. Descriptions below are copied from 'git log'.</li> + <li>Update .gitignore for new dependencies.</li> + <li>Use a submodule for i945-pwm.</li> + <li>Don't clean packages that fail or don't need cleaning.</li> + <li>Don't clean i945-pwm, it's not needed.</li> + <li>Regression fix: Parabola live ISO boot issues</li> + <li>Re-enable background images in ISOLINUX/SYSLINUX GRUB parser menus</li> + <li>Regression fix: Re-add CD-ROM (ata0) in GRUB</li> + <li>Documentation: add notes about performance penalty when using ecryptfs.</li> + <li>Documentation: Fixed spelling and grammatical errors.</li> + <li>Documentation: macbook21: add new system as tested</li> + <li>Documentation: macbook21: add info about improving touchpad sensitivity</li> + <li>Documentation: X60 Tablet: add more information about finger input</li> + <li>Documentation: release.html: Add information about recently merged commit in coreboot</li> + </ul> + + <h2> + Revisions for r20140903 (6th beta) (3rd September 2014) + </h2> + <ul> + <li>Added modified builddeb* scripts for Parabola GNU/Linux-libre: buildpac, buildpac-flashrom, buildpac-bucts (courtesy of Noah Vesely)</li> + <li>Documentation: updated all relevant areas to mention use of buildpac* scripts for Parabola users.</li> + <li>Documentation: added information showing how to enable or disable bluetooth on the X60</li> + <li>MacBook1,1 tested! See <b>hcl/index.html#macbook11</b></li> + <li>Documentation: fixed typo in index.html#get_edid_panelname (get-edit changed to get-edid)</li> + <li>Documentation: added images/x60_lcd_change/ (pics only for now)</li> + <li>Added gcry_serpent and gcry_whirlpool to the GRUB module list in the 'build' script (for luks users)</li> + <li> + <b>Libreboot is now based on a new coreboot version from August 23rd, 2014:<br/> + Merged commits (relates to boards that were already supported in libreboot):</b> + <ul> + <li><a href="http://review.coreboot.org/#/c/6697/">http://review.coreboot.org/#/c/6697/</a></li> + <li><a href="http://review.coreboot.org/#/c/6698/">http://review.coreboot.org/#/c/6698/</a> (merged already)</li> + <li><a href="http://review.coreboot.org/#/c/6699/">http://review.coreboot.org/#/c/6699/</a> (merged already)</li> + <li><a href="http://review.coreboot.org/#/c/6696/">http://review.coreboot.org/#/c/6696/</a> (merged already)</li> + <li><a href="http://review.coreboot.org/#/c/6695/">http://review.coreboot.org/#/c/6695/</a> (merged already)</li> + <li><b><a href="http://review.coreboot.org/#/c/5927/">http://review.coreboot.org/#/c/5927/</a> (merged already)</b></li> + <li><a href="http://review.coreboot.org/#/c/6717/">http://review.coreboot.org/#/c/6717/</a> (merged already)</li> + <li><a href="http://review.coreboot.org/#/c/6718/">http://review.coreboot.org/#/c/6718/</a> (merged already)</li> + <li> + <a href="http://review.coreboot.org/#/c/6723/">http://review.coreboot.org/#/c/6723/</a> (merged already) + (text-mode patch, might enable memtest. macbook21) + </li> + <li> + <a href="http://review.coreboot.org/#/c/6732/">http://review.coreboot.org/#/c/6732/</a> (MERGED) + (remove useless ps/2 keyboard delay from macbook21. already merged) + </li> + </ul> + </li> + <li> + These were also merged in coreboot (relates to boards that libreboot already supported): + <ul> + <li><a href="http://review.coreboot.org/#/c/5320/">http://review.coreboot.org/#/c/5320/</a> (merged)</li> + <li><a href="http://review.coreboot.org/#/c/5321/">http://review.coreboot.org/#/c/5321/</a> (merged)</li> + <li><a href="http://review.coreboot.org/#/c/5323/">http://review.coreboot.org/#/c/5323/</a> (merged)</li> + <li><a href="http://review.coreboot.org/#/c/6693/">http://review.coreboot.org/#/c/6693/</a> (merged)</li> + <li><a href="http://review.coreboot.org/#/c/6694/">http://review.coreboot.org/#/c/6694/</a> (merged)</li> + <li><a href="http://review.coreboot.org/#/c/5324/">http://review.coreboot.org/#/c/5324/</a> (merged)</li> + </ul> + </li> + <li>Documentation: removed the section about tft_brightness on X60 (new code makes it obsolete)</li> + <li>Removed all patches from resources/libreboot/patch/ and added new patch: 0000_t60_textmode.git.diff</li> + <li>Updated getcb script and DEBLOB script.</li> + <li>Updated configuration files under resources/libreboot/config/ to accomodate new coreboot version.</li> + <li> + Removed grub_serial*.cfg and libreboot_serial*.rom, all configs/rom files are now unified (containing same configuration as serial rom files from before). + <ul> + <li>Documentation: updated index.html#rom to reflect the above.</li> + </ul> + </li> + <li>Updated GRUB to new version from August 14th, 2014.</li> + <li>Unified all grub configurations for all systems to a single grub.cfg under resources/grub/config/</li> + <li>Updated flashrom to new version from August 20th, 2014</li> + <li> + Added getseabios and builddeps-seabios (builddeps and getall were also updated) + <ul> + <li> + Added instructions to 'buildrom-withgrub' to include bios.bin.elf and vgaroms/vgabios.bin from SeaBIOS inside the ROM. + </li> + </ul> + </li> + <li>Added seabios (and sgavgabios) to grub as payload option in menu</li> + <li> + Disabled serial output in Memtest86+ (no longer needed) to speed up tests. + <ul> + <li>MemTest86+ now works properly, it can output on the laptop screen (no serial port needed anymore).</li> + </ul> + </li> + <li> + Added getgrubinvaders, builddeps-grubinvaders scripts. Added these to getall and builddeps. + <ul> + <li> + Added <a href="http://www.coreboot.org/GRUB_invaders">GRUB Invaders</a> menu entry in resources/grub/config/grub.cfg + </li> + </ul> + </li> + <li>Added rules to builddeps-coreboot to build libpayload with TinyCurses. (added appropriate instructions to cleandeps script).</li> + <li>Commented out lines in resources/grub/config/grub.cfg for loading font/background (not useful anymore, now that GRUB is in text-mode).</li> + <li>Commented out lines in buildrom-withgrub that included backgrounds/fonts (not useful anymore, now that GRUB is in text-mode).</li> + <li> + Added resources/utilities/i945-pwm/ (from git://git.mtjm.eu/i945-pwm), for debugging acpi brightness on i945 systems. + <ul> + <li>Added instructions for it in builddeps, builddeps-i945pwm, builddeb and cleandeps</li> + </ul> + </li> + <li>'build' script: removed the parts that generated sha512sum manifests (not needed, since release tarballs are GPG-signed)</li> + <li> + 'build' script: removed the parts that generated libreboot_meta directory (not needed anymore, since _meta will be hosted in git) + <ul> + <li>Updated index.html#build_meta (and other parts of documentation) to accomodate this change.</li> + </ul> + </li> + <li>Documentation: simplified (refactored) the notes in index.html#rom</li> + <li> + 'build' script: removed the parts that generated libreboot_bin and added them to a new script: 'build-release' + <ul> + <li>Documentation: index.html#build updated to reflect the above.</li> + </ul> + </li> + <li>Removed 'sudo' from builddeb, builddeb-flashrom, powertop.trisquel6 and builddeb-bucts scripts (assuming that the user has it is a really bad idea).</li> + <li><s>Added all gcry_* modules to grub (luks/cryptomount): gcry_arcfour gcry_camellia gcry_crc gcry_dsa gcry_md4 gcry_rfc2268 gcry_rmd160 gcry_seed gcry_sha1 gcry_sha512 gcry_twofish gcry_blowfish gcry_cast5 gcry_des gcry_idea gcry_md5 gcry_rijndael gcry_rsa gcry_serpent gcry_sha256 gcry_tiger gcry_whirlpool</s></li> + <li>Added GNUtoo's list of GRUB modules (includes all of the gcry_* modules above), cryptomount should be working now.</li> + <li>Removed builddeb-bucts and builddeb-flashrom, merged them with builddeb (index.html updated accordingly)</li> + <li>Removed buildpac-bucts and buildpac-flashrom, merged them with buildpac (index.html updated accordingly)</li> + <li>Renamed builddeb to deps-trisquel (index.html updated accordingly)</li> + <li>Renamed buildpac to deps-parabola (index.html updated accordingly)</li> + <li>Documentation: removed all parts talking about build dependencies, replaced them with links to index.html#build_dependencies</li> + <li>Documentation: emphasized more strongly on the documentation, the need to re-build bucts and/or flashrom before flashing a ROM image.</li> + <li>build-release: flashrom, nvramtool, cbfstool and bucts are no longer provided pre-compiled in binary archives, and are now in source form only. (to maximize distro compatibility).</li> + <li>Documentation: added gnulinux/encrypted_trisquel.html showing how to setup a fully encrypted Trisquel installation (including /boot) and boot it from the GRUB payload.</li> + <li>'build' script: replaced grub.elf assembly instructons, it is now handled by a utility added under resources/utilities/grub-assemble</li> + <li>Moved resources/grub/keymap to resources/utilities/grub-assemble/keymap, and updated that utility to use it</li> + <li>Documentation: removed useless links to pictures of keyboard layouts and unmodified layouts.</li> + <li>Removed all unused fonts from dejavu-fonts-ttf-2.34/ directory</li> + <li>'buildrom-withgrub' script: updated it to create 2 sets of ROMs for each system: one with text-mode, one with coreboot framebuffer.</li> + <li>Documentation: updated index.html#rom to reflect the above</li> + <li>Deleted unused README and COPYING file from main directory</li> + <li>Removed some rm -Rf .git* instructions from the get* scripts and moved them to build-release script</li> + <li> + Split up default grub.cfg into 6 parts: extra/{common.cfg,txtmode.cfg,vesafb.cfg} and menuentries/{common.cfg,txtmode.cfg,vesafb.cfg} + <ul> + <li>buildrom-withgrub script uses these to generate the correct grub.cfg for each type of configuration.</li> + </ul> + </li> + <li>grub_memdisk.cfg (used inside grub.elf) now only loads grub.cfg from cbfs. It no longer enables serial output or sets prefix. (menuentries/common.cfg does instead)</li> + <li> + resources/grub/config/extra/common.cfg, added: + <ul> + <li>insmod instructions to load those modules: nativedisk, ehci, ohci, uhci, usb, usbserial_pl2303, usbserial_ftdi, usbserial_usbdebug</li> + <li>set prefix=(memdisk)/boot/grub</li> + <li> + For native graphics (recommended by coreboot wiki):<br/> + gfxpayload=keep<br/> + terminal_output --append gfxterm + </li> + <li> + Play a beep on startup:<br/> + play 480 440 1 + </li> + </ul> + </li> + <li> + Documentation: added note about 'fb=false' workaround for text-mode debian-installer (Trisquel net install) to + gnulinux/grub_boot_installer.html + </li> + <li> + Documentation: updated gnulinux/grub_cbfs.html to make it safer (and easier) to follow. + </li> + </ul> + + <h2> + Corrections to r20140811 (5th beta) (11th August 2014) + </h2> + <ul> + <li>Fixed typo where revision list for 5th beta was listed as March 11th 2014, when in fact it was August 11th 2014</li> + <li>Fixed incorrect grub.cfg that was actually placed in resources/grub/config/x60/grub_usqwerty.cfg which broke the default GRUB menu entry on X60</li> + </ul> + + <h2> + Revisions for r20140811 (5th beta) (11th August 2014) + </h2> + <ul> + <li>build: added 'luks', 'lvm', 'cmosdump' and 'cmostest' to the list of modules for grub.elf</li> + <li>Documentation: added pics showing T60 unbricking (still need to write a tutorial)</li> + <li>build: include cmos.layout (coreboot/src/mainboard/manufacturer/model/cmos.layout) files in libreboot_bin</li> + <li>Documentation: added <b>install/x60tablet_unbrick.html</b></li> + <li>Documentation: added <b>install/t60_unbrick.html</b></li> + <li>Documentation: added <b>install/t60_lcd_15.html</b></li> + <li>Documentation: added <b>install/t60_security.html</b></li> + <li>Documentation: added <b>install/t60_heatsink.html</b></li> + <li>Documentation: Renamed RELEASE.html to release.html</li> + <li>Documentation: removed pcmcia reference in x60_security.html (it's cardbus)</li> + <li>Documentation: added preliminary information about randomized seal (for physical intrusion detection) in x60_security.html and t60_security.html</li> + <li>Documentation: added preliminary information about preventing/mitigating cold-boot attack in x60_security.html and t60_security.html</li> + <li>Documentation: added info to index.html#macbook21 warning about issues with macbook21</li> + <li> + Documentation: X60/T60: added information about checking custom ROMs using dd to see whether or not the top 64K + region is duplicated below top or not. Advise caution about this in the tutorial that deals with flashing on top + of Lenovo BIOS, citing the correct dd commands necessary if it is confirmed that the ROM has not been applied with + dd yet. (in the case that the user compiled their own ROMs from libreboot, without using the build scripts, or if they forgot to use dd, etc). + </li> + <li> + Split resources/libreboot/patch/gitdiff into separate patch files (getcb script updated to accomodate this change). + </li> + <li>Re-added .git files to bucts</li> + <li>Fixed the oversight where macbook21_firstflash wasn't included in binary archives</li> + <li>Release archives are now compressed using .tar.xz for better compression</li> + </ul> + + <h2> + Revisions for r20140729 (4th beta) (29th July 2014) + </h2> + <ul> + <li>Documentation: improved (more explanations, background info) in docs/security/x60_security.html (courtesy of Denis Carikli)</li> + <li>MacBook2,1 tested (confirmed)</li> + <li>macbook21: Added script 'macbook21_firstflash' for flashing libreboot while Apple EFI firmware is running.</li> + <li>Documentation: macbook21: added software-based flashing instructions for flashing libreboot while Apple EFI firmware is running.</li> + <li> + Reduced size of libreboot_src.tar.gz: + <ul> + <li> + Removed .git and .gitignore from grub directory (libreboot_src); not needed. + Removing them reduces the size of the archive (by a lot). GRUB development should be upstream. + </li> + <li> + Removed .git and .gitignore from bucts directory (libreboot_src); not needed. + Removing them reduces the size of the archive. bucts development should be upstream. + </li> + <li> + Removed .svn from flashrom directory (libreboot_src); not needed. + Removing it reduces the size of the archive. flashrom development should be upstream. + </li> + </ul> + </li> + <li> + Added ROMs with Qwerty (Italian) layout in GRUB (libreboot*itqwerty.rom) + </li> + <li> + Added resources/utilities/i945gpu/intel-regs.py for debugging issues related to LCD panel compatibility on X60 Tablet and T60. (courtesy of <a href="http://mtjm.eu">Michał Masłowski</a>) + </li> + </ul> + + <h2> + Revisions for r20140720 (3rd beta) (20th July 2014) + </h2> + <ul> + <li> + Fixed typo that existed in 2nd beta where the release date of the 2nd beta was listed as being in year 2016, when in actual fact it was 2014. + </li> + <li> + Documentation: added (preliminary) details about (rare) buggy CPUs on the ThinkPad T60 that were found to fail (instability, kernel panics, etc) + without the microcode updates. + </li> + <li>Documentation: added docs/hardware/x60_heatsink.html for showing how to change the heatsink on the Thinkpad X60</li> + <li>Added ROM images for Azerty (French) keyboard layout in GRUB (courtesy of Olivier Mondoloni)</li> + <li> + Tidied up some scripts: + <ul> + <li><s>Re-factored those scripts (made easier to read/maintain): build-x60, build-x60t, build-t60, build-macbook21</s></li> + <li><s>Reduced the number of grub configs to 2 (or 1, for macbook21), the build scripts now generate the other configs at build time.</s></li> + <li>Deleted build-x60, build-x60t, build-t60, build-macbook21 and replaced with intelligent (generic) buildrom-withgrub script</li> + <li>Updated build to use buildrom-withgrub script for building the ROM images.</li> + <li>coreboot.rom and coreboot_serial.rom renamed to coreboot_usqwerty.rom and coreboot_serial_usqwerty.rom</li> + <li>coreboot_dvorak and coreboot_serial_dvorak.rom renamed to coreboot_usdvorak.rom and coreboot_serial_usdvorak.rom</li> + <li>Renamed coreboot*rom to libreboot*rom</li> + <li>Made flash, lenovobios_firstflash and lenovobios_secondflash scripts fail if the specified file does not exist.</li> + <li>Updated all relevant parts of the documentation to reflect the above.</li> + </ul> + </li> + <li>Replaced background.png with background.jpg. added gnulove.jpg. (resources/grub/background/)</li> + <li>Updated buildrom-withgrub to use background.jpg instead of background.png</li> + <li>Updated buildrom-withgrub to use gnulove.jpg aswell</li> + <li>Updated resources/grub/config/macbook21/grub*cfg to use gnulove.jpg background.</li> + <li>Updated resources/grub/config/{x60,t60,x60t}/grub*cfg to use background.jpg background.</li> + <li>Documentation: updated docs/index.html#grub_custom_keyboard to be more generally useful.</li> + <li> + nvramtool: + <ul> + <li>Updated builddeps-coreboot script to build it</li> + <li>Updated build script to include it in libreboot_bin</li> + </ul> + </li> + <li> + Documentation: added docs/security/x60_security.html (security hardening for X60) + </li> + </ul> + + <h2> + Revisions for r20140716 (2nd beta) (16th July 2014) + </h2> + <ul> + <li> + Deleted all git-related files from the coreboot directory. This was necessary because + with those it is possible to run 'git diff' which shows the changes made in the form + of a patch (diff format); this includes the blobs that were deleted during deblobbing. + </li> + </ul> + + <h2> + Revisions for r20140711 (1st beta) (11th July 2014) + </h2> + <ul> + <li>Initial release (new coreboot base, dated 1st June 2014. See 'getcb' script for reference)</li> + <li>DEBLOBBED coreboot</li> + <li>Removed the part from memtest86+ 'make' where it tried to connect to some scp server while compiling. (commented out line 24 in the Makefile)</li> + <li>X60 now uses a single .config (for coreboot)</li> + <li>X60 now uses a single grub.cfg (for grub memdisk)</li> + <li>X60 now uses a single grub.elf (payload)</li> + <li>Added new native graphics code for X60 (replaces the old 'replay' code) from Vladimir Serbinenko: 5320/9 from review.coreboot.org</li> + <li>T60 is now supported, with native graphics. (5345/4 from review.coreboot.org, cherry-picked on top of 5320/9 checkout)</li> + <li> + Added macbook2,1 support (from Mono Moosbart and Vladimir Serbinenko) from review.coreboot.org (see 'getcb' script to know how that was done) + <ul> + <li>Documentation: added information linking to correct page and talking about which models are supported.</li> + <li>Added resources/libreboot/config/macbook21config</li> + <li>macbook21: Added 'build-macbook21' script and linked to it in 'build' (ROMs included under bin/macbook21/)</li> + <li>macbook21: Removed dd instructions from build-macbook21 script (macbook21 does not need bucts when flashing libreboot while Apple EFI firmware is running)</li> + <li>Documentation: Added macbook21 ROMs to the list of ROMs in docs/index.html#rom</li> + <li>Documentation: Write documentation linking to Mono Moosbart's macbook21 and parabola page (and include a copy)</li> + </ul> + </li> + <li>Documentation: added a copy of Mono's Parabola install guide (for macbook21 with Apple EFI firmware) and linked in in main index.</li> + <li>Documentation: added a copy of Mono's Coreboot page (for macbook21) and linked it in main index.</li> + <li>T60: Copy CD option from the grub.cfg files for T60 *serial*.rom images into the grub configs for non-serial images. (T60s have CD/DVD drive on main laptop)</li> + <li>macbook21: remove options in build-macbook21 for *serial*.rom (there is no dock or serial port available for macbook21)</li> + <li> + Added patches for backlight controls on X60 and T60 with help from Denis Carikli (see ./resources/libreboot/patch/gitdiff and ./getcb and docs/i945_backlight.html) + <ul> + <li>Documentation: added docs/i945_backlight.html showing how backlight controls were made to work on X60/T60</li> + </ul> + </li> + <li> + Documentation: Added info about getting LCD panel name based on EDID data. + <ul> + <li>Documentation: Added a link to this from the list of supported T60s and LCD panels for T60 (so that the user can check what LCD panel they have).</li> + </ul> + </li> + <li> + X60/T60: Merged patches for 3D fix (from Paul Menzel) when using kernel 3.12 or higher (see ./resources/libreboot/patch/gitdiff and ./getcb) + <ul> + <li>based on 5927/11 and 5932/5 from review.coreboot.org</li> + </ul> + </li> + <li> + Improved thinkpad_acpi support (from coreboot ): xsensors shows more information. + <ul> + <li>From 4650/29 in review.coreboot.org (merged in coreboot 'master' on June 1st 2014)</li> + </ul> + </li> + <li> + Merged changes for digitizer (X60 Tablet) and IR (X60 and T60) based on 5243/17, 5242/17 and 5239/19 from review.coreboot.org + <ul> + <li>(see ./resources/libreboot/patch/gitdiff and ./getcb)</li> + </ul> + </li> + <li>Documentation: added information about building flashrom using 'builddeps-flashrom' script.</li> + <li>Re-created resources/libreboot/config/x60config</li> + <li>Re-created resources/libreboot/config/t60config</li> + <li> + Added 'x60tconfig' in resources/libreboot/config (because X60 Tablet has different information about serial/model/version in 'dmidecode') + <ul> + <li>Added 'build-x60t' script</li> + <li>Updated 'build' script to use 'build-x60t'</li> + <li>Documentation: added to #config section the section #config_x60t (libreboot configuration and dmidecode info)</li> + <li>Documentation: added x60t ROMs to the list of ROMs</li> + </ul> + </li> + <li>Tidied up the 'builddeps' script (easier to read)</li> + <li>Tidied up the 'cleandeps' script (easier to read)</li> + <li>Annotated the 'buildall' script</li> + <li>Added 'getcb' script for getting coreboot revision used from git, and patching it.</li> + <li>Added 'getgrub' script for getting the GRUB revision used from git, and patching it.</li> + <li>Added 'getmt86' script for getting the memtest86+ version used, and patching it.</li> + <li>Added 'getbucts' script for getting the bucts version used.</li> + <li>Added 'getflashrom' script for getting the flashrom version used, and patching it</li> + <li>Added 'getall' script which runs all of the other 'get' scripts.</li> + <li> + Add instructions to the 'build' script to prepare libreboot_meta.tar.gz + <ul> + <li>New archive: libreboot_meta.tar.gz - minimal archive, using the 'get' scripts to download all the dependencies (coreboot, memtest, grub and so on).</li> + </ul> + </li> + <li>Documentation: added information about where 'build' script prepares the libreboot_meta.tar.gz archive.</li> + <li> + Documentation: added information about how to use the 'get' scripts in libreboot_meta.tar.gz (to generate libreboot_src.tar.gz) + <ul> + <li>Documentation: mention that meta doesn't create libreboot_src/ directory, but that libreboot_meta itself becomes the same.</li> + <li>Documentation: advise to rename libreboot_meta to libreboot_src after running 'getall'.</li> + </ul> + </li> + <li>Annotated the 'builddeb' script, to say what each set of dependencies are for.</li> + <li>Separated bucts/flashrom builddeb sections into separate scripts: builddeb-flashrom, builddeb-bucts.</li> + <li>Documentation: Updated relevant parts based on the above.</li> + <li>Added instructions to 'build' script for including builddeb-bucts and builddeb-flashrom in libreboot_bin</li> + <li> + Updated flashrom checkout (r1822 2014-06-16) from SVN (http://flashrom.org/Downloads). + <ul> + <li>Updated flashing instructions in docs/index.html for new commands needed (Macronix chip on X60/T60)</li> + <li>For X60/T60 (flashrom): Patched flashchips.c_lenovobios_macronix and flashchips.c_lenovobios_sst executables for SST/macronix (included in resources/flashrom/patch)</li> + <li>Updated builddeps to build flashrom_lenovobios_sst and flashrom_lenovobios_macronix, for X60/T60 users with Lenovo BIOS</li> + <li>moved the flashrom build instructions from 'builddeps' and put them in 'builddeps-flashrom', excecuting that from 'builddeps'.</li> + <li>Added builddeps-flashrom to libreboot_bin.tar.gz</li> + </ul> + </li> + <li> + flashrom: added patched flashchips.c to resources/flashrom/patch (automatically use correct macronix chip on libreboot, without using '-c' switch) + <ul> + <li>removed 'MX25L1605' and 'MX25L1605A/MX25L1606E' entries in flashchips.c for the patched version of flashchips.c</li> + <li>added instructions to 'builddeps-flashrom' to automatically use this modified flashchips.c in the default build</li> + </ul> + </li> + <li>Added builddeb to libreboot_bin.tar.gz</li> + <li> + Moved 'bucts' build instructions from builddeps to builddeps-bucts + <ul> + <li>builddeps now runs 'builddeps-bucts' instead</li> + <li>Added 'builddeps-bucts' to libreboot_bin.tar.gz</li> + <li>Documentation: Added information about using 'builddep-bucts' to build the BUC.TS utility.</li> + </ul> + </li> + <li> + Added 'lenovobios_firstflash' and 'lenovobios_secondflash' scripts + <ul> + <li>Added instructions to 'build' script for including those files in libreboot_bin</li> + <li>Documentation: Add tutorial for flashing while Lenovo BIOS is running (on X60/T60)</li> + </ul> + </li> + <li> + Added 'flash' script (make sure to run builddeps-flashrom first) which (while libreboot is already running) can use flashrom to flash a ROM + <ul> + <li>eg: &quot;sudo ./flash bin/x60/coreboot_serial_ukdvorak.rom&quot; equivalent to &quot;sudo ./flashrom/flashrom -p internal -w bin/x60/coreboot_uk_dvorak.rom&quot;</li> + <li>updated 'build' script to include the 'flash' script in libreboot_bin.tar.gz</li> + </ul> + </li> + <li>Documentation: replaced default flashrom tutorial to recommend the 'flash' script instead.</li> + <li> + Re-add cbfstool source code back into libreboot_bin.tar.gz, as cbfstool_standalone + <ul> + <li>Patched that version to work (able to be built and used) without requiring the entire coreboot source code.</li> + <li> + Created patched version of the relevant source files and added it into resources/cbfstool/patch + <ul> + <li>see coreboot/util/cbfstool/rmodule.c and then the patched version in resources/cbfstool/patch/rmodule.c</li> + <li>see coreboot/src/include/rmodule-defs.h and the rule in 'build' for including this in ../libreboot_bin/cbfstool_standalone</li> + </ul> + </li> + <li>Added instructions to 'build' script for applying this patch to the cbfstool_standalone source in libreboot_bin</li> + <li>Added instructions to 'build' script for then re-compiling cbfstool_standalone in libreboot_bin after applying the patch</li> + <li>Added a 'builddeps-cbfstool' script (in src, but only used in bin and put in bin by 'build') that compiles cbfstool_standalone in libreboot_bin (make), moves the cbfstool and rmodtool binaries into libreboot_bin/ and then does 'make clean' in libreboot_bin/cbfstool_standalone</li> + <li>Updated the 'build' script to put 'builddeps-cbfstool' in libreboot_bin</li> + <li>Updated the 'build' script in the cbfstool (standalone) part to accomodate the above.</li> + <li>Documentation: added notes about cbfstool (standalone) in libreboot_bin</li> + </ul> + </li> + <li>Documentation: made docs/gnulinux/grub_cbfs.html slightly easier to follow.</li> + <li>Annotate the 'build*' scripts with 'echo' commands, to help the user understand what it actually happening during the build process.</li> + <li> + Documentation: added information about how 'dmidecode' data was put in the coreboot configs + <ul> + <li>Documentation: In fact, document how the 'config' files in resources/libreboot/config/ were created</li> + </ul> + </li> + <li>Documentation: Added information about which ThinkPad T60s are supported, and which are not.</li> + <li> + Documentation: added information about LCD inverters (for upgrading the LCD panel on a T60 14.1' XGA or 15.1' XGA) + <ul> + <li>it's FRU P/N 41W1478 (on T60 14.1&quot;) so this was added to the docs.</li> + <li>it's P/N 42T0078 FRU 42T0079 or P/N 41W1338 (on T60 15.1&quot;) so this was added to the docs.</li> + </ul> + </li> + <li>Documentation: added information about names of LCD panels for T60 to the relevant parts of the documentation.</li> + <li>Documentation: added information (with pictures) about the differences between T60 with Intel GPU and T60 with ATI GPU.</li> + <li>Documentation: added pictures of keyboard layouts (US/UK Qwerty/Dvorak) to the ROM list, to let the user compare with their own keyboard.</li> + <li> + Move the coreboot build instructions in 'builddeps' into 'builddeps-coreboot' and link it in 'builddeps' + <ul> + <li>Link to 'builddeps-coreboot' in final stage of 'getcb'</li> + </ul> + </li> + <li> + Move GRUB build instructions from 'builddeps' into 'builddeps-grub', link from 'builddeps' + <ul> + <li>Link to 'builddeps-grub' in final stage of 'getgrub'</li> + </ul> + </li> + <li> + Move MemTest86+ build instructions from 'builddeps' into 'builddeps-memtest86', link from 'builddeps' + <ul> + <li>Link to 'builddeps-memtest86' in final stage of 'getmt86'</li> + </ul> + </li> + <li>made 'build' script put resources/ directory in libreboot_bin, to make builddeps-flashrom work in libreboot_bin</li> + <li>Removed instructions for building source code in the 'get' script (they don't really belong there)</li> + <li>Added libfuse-dev and liblzma-dev to the list of GRUB dependencies in 'builddeb' script.</li> + <li>Converted the 'RELEASE' file to 'docs/RELEASE.html'</li> + <li>Added those dependencies to builddeb script (for GRUB part): gawk libdevmapper-dev libtool libfreetype6-dev</li> + <li>Added to build script the instruction at the end to create a sha512sum.txt with a file manifest plus checksums.</li> + <li>Deleted the RELEASE and BACKPORT files (no longer needed)</li> + <li> + Documentation: added information about X60/T60 dock (ultrabase x6 and advanced mini dock) to relevant sections. + <ul> + <li>Added to docs/index.html#serial</li> + </ul> + </li> + </ul> + + <p><a href="#pagetop">Back to top of page.</a></p> + + </div> + + <div class="section"> + + <h1 id="release20140622">Release 20140622 (5th release)</h1> + + <ul> + <li>7th March 2014</li> + <li>revised 22nd June 2014</li> + </ul> + + <h2>Officially supported</h2> + <ul> + <li>ThinkPad X60</li> + <li>ThinkPad X60s</li> + </ul> + + <h2>Revision (22nd June 2014 - extra)</h2> + <ul> + <li>Documentation: added X60 Unbricking tutorial</li> + <li>Documentation: added info about enabling or disabling wifi</li> + <li>Documentation: added info about enabling or disabling trackpoint</li> + </ul> + + <h2>Revision (22nd June 2014 - extra)</h2> + <ul> + <li>Documentation: Improved the instructions for using flashrom</li> + <li>Documentation: Improved the instructions for using cbfstool (to change the default GRUB menu)</li> + <li>Documentation: Numerous small fixes.</li> + </ul> + + <h2>Revision notes (22nd June 2014)</h2> + <ul> + <li>updated GRUB (git 4b8b9135f1676924a8458da528d264bbc7bbb301, 20th April 2014)</li> + <li>Made &quot;DeJavu Sans Mono&quot; the default font in GRUB (fixes border corruption).</li> + <li>re-added background image in GRUB (meditating GNU)</li> + <li> + added 6 more images: + <ul> + <li>coreboot_ukqwerty.rom (UK Qwerty keyboard layout in GRUB)</li> + <li>coreboot_serial_ukqwerty.rom (UK Qwerty keyboard layout in GRUB)</li> + <li>coreboot_dvorak.rom (US Dvorak keyboard layout in GRUB)</li> + <li>coreboot_serial_dvorak.rom (US Dvorak keyboard layout in GRUB)</li> + <li>coreboot_ukdvorak.rom (UK Dvorak keyboard layout in GRUB)</li> + <li>coreboot_serial_ukdvorak.rom (UK Dvorak keyboard layout in GRUB)</li> + <li>(coreboot.rom and coreboot_serial.rom have US Qwerty keyboard layout in GRUB, as usual)</li> + </ul> + </li> + <li> + improved the documentation: + <ul> + <li>removed FLASH_INSTRUCTION and README.powertop and merged them with README</li> + <li>removed obsolete info from README and tidied it up</li> + <li>deleted README (replaced with docs/index.html)</li> + </ul> + </li> + <li>tidied up the menu entries in GRUB</li> + <li>tidied up the root directory of X60_source/, sorted more files into subdirectories</li> + <li>added 'pkg-config' to the list of dependencies for building powertop on Trisquel</li> + <li>wrote a script (powertop.trisquel6) to automatically setup Powertop to run at boot time (for Trisquel 6 users)</li> + <li>improved the commenting inside the 'build' script (should make modifying it easier)</li> + <li>Renamed X60_binary.tar.gz and X60_source.tar.gz to libreboot_bin.tar.gz and libreboot_src.tar.gz, respectively.</li> + <li>Replaced &quot;GNU GRUB version&quot; with &quot;FREE AS IN FREEDOM&quot; on GNU GRUB start screen.</li> + <li>Added sha512.txt files in libreboot_src and libreboot_bin. (inside the archives)</li> + <li>Added libreboot_bin.tar.gz.sha512.txt and libreboot_src.tar.gz.sha512.txt files (outside of the archives)</li> + </ul> + + <h2>Revision notes (11th June 2014):</h2> + <ul> + <li>removed 'CD' boot option from coreboot.rom (not needed)</li> + <li>removed 'processor.max_cstate=2' and 'idle=halt' options (see README.powertop file)</li> + </ul> + + <h2>Revision notes (5th June 2014):</h2> + <ul> + <li>added backlight support (Fn+Home and Fn+End) on X60</li> + <li>fixed broken/unstable 3D when using kernel 3.12 or higher</li> + <li>(see 'BACKPORT' file)</li> + </ul> + + <h2>Revision notes (9th March 2015):</h2> + <ul> + <li>recreated coreboot config from scratch</li> + <li>GRUB loads even faster now (less than 2 seconds).</li> + <li>Total boot time reduced by further ~5 seconds.</li> + <li>Added crypto and cryptodisk modules to GRUB</li> + <li>cbfstool now included in the binary archives</li> + </ul> + + <h2>Development notes</h2> + <ul> + <li> + Binary archive now have 2 images: + <ul> + <li>With serial output enabled and memtest86+ included (debug level 8 in coreboot)</li> + <li>With serial output disabled and memtest86+ excluded (faster boot speeds) (debugging disabled)</li> + </ul> + </li> + <li> + Reduced impact on battery life: + <ul> + <li>'processor.max_cstate=2' instead of 'idle=halt' for booting default kernel</li> + </ul> + </li> + <li> + coreboot.rom (faster boot speeds, debugging disabled): + <ul> + <li>Disabled coreboot serial output (Console-> in &quot;make menuconfig&quot;)</li> + <li>Set coreboot debug level to 0 instead of 8 (Console-> in &quot;make menuconfig&quot;)</li> + <li>Changed GRUB timeout to 1 second instead of 2 (in grub.cfg</li> + <li>Removed background image in GRUB.</li> + <li>Removed memtest86+ payload (since it relies on serial output) + </ul> + </li> + <li> + coreboot_serial.rom (slower boot speeds, debugging enabled): + <ul> + <li>Boot time still reduced, but only by ~2 seconds</li> + <li>has the memtest86+ payload included in the ROM</li> + <li>has serial port enabled. How this is achieved (from X60_source): Turn on debugging level to 8, and enable serial output</li> + </ul> + </li> + <li>(in Console-> in coreboot &quot;make menuconfig&quot;)</li> + <li>(and build with grub_serial.cfg and grub_memdisk_serial.cfg)</li> + </ul> + + <p><a href="#pagetop">Back to top of page.</a></p> + + </div> + + <div class="section"> + + <h1 id="release20140221">Release 20140221 (4th release)</h1> + + <ul> + <li>21st February 2014</li> + </ul> + + <h2>Officially supported</h2> + <ul> + <li>ThinkPad X60</li> + <li>ThinkPad X60s</li> + </ul> + + <h2>Development notes</h2> + <ul> + <li>Removed SeaBIOS (redundant)</li> + <li> + New GRUB version (2.02~beta2) + <ul> + <li>Fixes some USB issues</li> + <li>Includes ISOLINUX/SYSLINUX parser</li> + </ul> + </li> + <li>New grub.cfg</li> + <li> + Removed useless options: + <ul> + <li>options for booting sda 2/3/4</li> + <li>seabios boot option</li> + </ul> + </li> + <li> + Added new menu entries: + <ul> + <li>Parse ISOLINUX config (USB)</li> + <li>Parse ISOLINUX config (CD)</li> + <li>Added 'cat' module for use on GRUB command line.</li> + </ul> + </li> + <li>&quot;set pager=1&quot; is set in grub.cfg, for less-like functionality</li> + </ul> + <p> + The "Parse" options read ./isolinux/isolinux.cfg on a CD or USB, + and automatically converts it to a grub config and switches to the boot menu of that distro. + This makes booting ISOs *much* easier than before. + </p> + + <p><a href="#pagetop">Back to top of page.</a></p> + + </div> + + <div class="section"> + + <h1 id="release20131214">r20131214 (3rd release)</h1> + + <ul> + <li>14th December 2013</li> + </ul> + + <h2>Supported:</h2> + <ul> + <li>ThinkPad X60</li> + <li>ThinkPad X60s</li> + </ul> + + <h2>Development notes</h2> + <ul> + <li>Added SeaBIOS payload to GRUB2 (for booting USB drives)</li> + <li>new grub.cfg</li> + </ul> + + <p><a href="#pagetop">Back to top of page.</a></p> + + </div> + + <div class="section"> + + <h1 id="release20131213">r20131213 (2nd release)</h1> + + <ul> + <li>13th December 2013</li> + </ul> + + <h2>Supported:</h2> + <ul> + <li>ThinkPad X60</li> + <li>ThinkPad X60s</li> + </ul> + + <h2>Development notes</h2> + <ul> + <li>added background image to GRUB2</li> + <li>added memtest86+ payload to grub2</li> + <li>improvements to the documentation</li> + <li>new grub.cfg</li> + </ul> + + <p><a href="#pagetop">Back to top of page.</a></p> + + </div> + + <div class="section"> + + <h1 id="release20131212">r20131212 (1st release)</h1> + + <ul> + <li>12th December 2013</li> + </ul> + + <h2>Supported:</h2> + <ul> + <li>ThinkPad X60</li> + <li>ThinkPad X60s</li> + </ul> + + <h2>Development notes</h2> + <ul> + <li>initial release</li> + <li>source code deblobbed</li> + </ul> + + <p><a href="#pagetop">Back to top of page.</a></p> + + </div> + + <div class="section"> + + <p> + Copyright &copy; 2014, 2015 Leah Rowe &lt;info@minifree.org&gt;<br/> + Permission is granted to copy, distribute and/or modify this document + under the terms of the GNU Free Documentation License, Version 1.3 + or any later version published by the Free Software Foundation; + with no Invariant Sections, no Front-Cover Texts, and no Back-Cover Texts. + A copy of the license can be found at <a href="gfdl-1.3.txt">gfdl-1.3.txt</a> + </p> + + <p> + Updated versions of the license (when available) can be found at + <a href="https://www.gnu.org/licenses/licenses.html">https://www.gnu.org/licenses/licenses.html</a> + </p> + + <p> + UNLESS OTHERWISE SEPARATELY UNDERTAKEN BY THE LICENSOR, TO THE + EXTENT POSSIBLE, THE LICENSOR OFFERS THE LICENSED MATERIAL AS-IS + AND AS-AVAILABLE, AND MAKES NO REPRESENTATIONS OR WARRANTIES OF + ANY KIND CONCERNING THE LICENSED MATERIAL, WHETHER EXPRESS, + IMPLIED, STATUTORY, OR OTHER. THIS INCLUDES, WITHOUT LIMITATION, + WARRANTIES OF TITLE, MERCHANTABILITY, FITNESS FOR A PARTICULAR + PURPOSE, NON-INFRINGEMENT, ABSENCE OF LATENT OR OTHER DEFECTS, + ACCURACY, OR THE PRESENCE OR ABSENCE OF ERRORS, WHETHER OR NOT + KNOWN OR DISCOVERABLE. WHERE DISCLAIMERS OF WARRANTIES ARE NOT + ALLOWED IN FULL OR IN PART, THIS DISCLAIMER MAY NOT APPLY TO YOU. + </p> + <p> + TO THE EXTENT POSSIBLE, IN NO EVENT WILL THE LICENSOR BE LIABLE + TO YOU ON ANY LEGAL THEORY (INCLUDING, WITHOUT LIMITATION, + NEGLIGENCE) OR OTHERWISE FOR ANY DIRECT, SPECIAL, INDIRECT, + INCIDENTAL, CONSEQUENTIAL, PUNITIVE, EXEMPLARY, OR OTHER LOSSES, + COSTS, EXPENSES, OR DAMAGES ARISING OUT OF THIS PUBLIC LICENSE OR + USE OF THE LICENSED MATERIAL, EVEN IF THE LICENSOR HAS BEEN + ADVISED OF THE POSSIBILITY OF SUCH LOSSES, COSTS, EXPENSES, OR + DAMAGES. WHERE A LIMITATION OF LIABILITY IS NOT ALLOWED IN FULL OR + IN PART, THIS LIMITATION MAY NOT APPLY TO YOU. + </p> + <p> + The disclaimer of warranties and limitation of liability provided + above shall be interpreted in a manner that, to the extent + possible, most closely approximates an absolute disclaimer and + waiver of all liability. + </p> + + </div> + +</body> +</html> diff --git a/docs/constants.texi b/docs/constants.texi @@ -0,0 +1,2 @@ +@set docsdir ../resources/ +@set useinstall diff --git a/docs/css/main.css b/docs/css/main.css @@ -0,0 +1,80 @@ +/* + + Main CSS stylesheet for libreboot.org (documentation section) + + Copyright (C) 2014, 2015 Leah Rowe <info@minifree.org> + + This program is free software: you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation, either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see <http://www.gnu.org/licenses/>. +*/ + +body { + background:#dfdfdf; + color:#2B2B2B; + font-family:Lato,sans-serif; + font-size:0.92em; + font-weight:400; + padding:0px; + margin:0px; +} +div.section { + background:#FFF; + border-radius:0.5em; + box-shadow: 0px 0px 5px 0px rgba(50, 50, 50, 0.75); + padding:1em; + margin:1em; +} +p, aside, li { + margin: 0.33em 0px 0.6em; + text-align:justify; +} +a { + color:#2B2BAA; + font-size:1.1em; +} +a:hover { + text-decoration:none; +} +h1,h2,h3 { + margin-bottom:0.2em; + margin-top:0.2em; +} +img { + max-width:100%; + height:auto; + border:solid 0.5em #fff; + border-radius:0.25em; + box-shadow: 0px 0px 5px 0px rgba(50, 50, 50, 0.75); + margin:0px; + padding:0px; + margin-right:1em; + margin-bottom:1em; +} + +p.lenovobios { + font-weight:bold; color:#f00; font-style:italic; font-size:1.2em; +} +p.lenovobios:hover { + color: #000; +} +div.important, pre, div.subsection { + padding:1em; + margin-bottom:1em; + background-color:#ece0e2; + border-radius:0.25em; + box-shadow: 0px 0px 5px 0px rgba(50, 50, 50, 0.75); +} + +.photos p { + text-align:left; +} diff --git a/docs/depthcharge/index.html b/docs/depthcharge/index.html @@ -0,0 +1,362 @@ +<!DOCTYPE html> +<html> +<head> + <meta charset="utf-8"> + <meta name="viewport" content="width=device-width, initial-scale=1"> + + <style type="text/css"> + @import url('../css/main.css'); + </style> + + <title>Depthcharge payload</title> +</head> + +<body> + + <div class="section"> + + <h1 id="pagetop">Depthcharge payload</h1> + + <p> + This section relates to the depthcharge payload used in libreboot. + </p> + + <p> + Or <a href="../index.html">Back to main index</a>. + </p> + + <ul> + <li><a href="#cros_security_model">CrOS security model</a></li> + <li><a href="#developer_mode_screen">Developer mode screen</a> + <ul> + <li><a href="#holding_developer_mode_screen">Holding the developer mode screen</li> + <li><a href="#booting_normally">Booting normally</li> + <li><a href="#booting_different_mediums">Booting from different mediums</li> + <li><a href="#showing_device_information">Showing device information</li> + <li><a href="#warnings">Warnings</li> + </ul> + </li> + <li><a href="#recovery_mode_screen">Recovery mode screen</a> + <ul> + <li><a href="#recovering_bad_state">Recovering from a bad state</a></li> + <li><a href="#enabling_developer_mode">Enabling developer mode</a></li> + </ul> + </li> + <li><a href="#configuring_verified_boot_parameters">Configuring verified boot parameters</a></li> + </ul> + + </div> + + <div class="section"> + + <h1 id="cros_security_model">CrOS security model</h1> + + <p> + CrOS (Chromium OS/Chrome OS) devices such as Chromebooks implement a strict security model to ensure that these devices do not become compromised, + that is implemented as the verified boot (vboot) reference, most of which is executed within depthcharge. + A detailed overview of the CrOS security model is available on the dedicated page. + </p> + + <div class="subsection"> + + <p> + In spite of the CrOS security model, depthcharge won't allow booting kernels without verifying their signature and booting from external media or legacy payload unless explicitly allowed: see <a href="#configuring_verified_boot_parameters">configuring verified boot parameters</a>. + </p> + + </div> + + </div> + + <div class="section"> + + <h1 id="developer_mode_screen">Developer mode screen</h1> + + <p> + The developer mode screen can be accessed in depthcharge when developer mode is enabled.<br /> + Developer mode can be enabled from the <a href="#recovery_mode_screen">recovery mode screen</a>. + </p> + + <p> + It allows booting normally, booting from internal storage, booting from external media (when enabled), booting from legacy payload (when enabled), showing information about the device and disabling developer mode. + </p> + + <div class="subsection"> + + <h2 id="holding_developer_mode_screen">Holding the developer mode screen</h2> + + <p> + As instructed on the developer mode screen, the screen can be held by pressing <b>Ctrl + H</b> in the first 3 seconds after the screen is shown. + After that delay, depthcharge will resume booting normally. + </p> + + </div> + + <div class="subsection"> + + <h2 id="booting_normally">Booting normally</h2> + + <p> + As instructed on the developer mode screen, a regular boot will happen after <b>3 seconds</b> (if developer mode screen is not held).<br /> + The default boot medium (internal storage, external media, legacy payload) is shown on screen. + </p> + + </div> + + <div class="subsection"> + + <h2 id="booting_different_mediums">Booting from different mediums</h2> + + <p> + Depthcharge allows booting from different mediums, when they are allowed (see <a href="#configuring_verified_boot_parameters">configuring verified boot parameters</a> to enable or disable boot mediums).<br /> + As instructed on the developer mode screen, booting from various mediums can be triggered by pressing various key combinations: + </p> + + <ul> + <li>Internal storage: <b>Ctrl + D</b></li> + <li>External media: <b>Ctrl + U</b> (when enabled)</li> + <li>Legacy payload: <b>Ctrl + L</b> (when enabled)</li> + </ul> + + </div> + + <div class="subsection"> + + <h2 id="showing_device_information">Showing device information</h2> + + <p> + As instructed on the developer mode screen, showing device information can be triggered by pressing <b>Ctrl + I</b> or <b>Tab</b>.<br /> + Various information is shown, including vboot non-volatile data, TPM status, GBB flags and key hashes.<br /> + </p> + + </div> + + <div class="subsection"> + + <h2 id="warnings">Warnings</h2> + + <p> + The developer mode screen will show warnings when: + + <ul> + <li>Booting kernels without verifying their signature is enabled</li> + <li>Booting from external media is enabled</li> + <li>Booting legacy payloads is enabled</li> + </ul> + + </p> + + </div> + + </div> + + <div class="section"> + + <h1 id="recovery_mode_screen">Recovery mode screen</h1> + + <p> + The recovery mode screen can be accessed in depthcharge, by pressing <b>Escape + Refresh + Power</b> when the device is off. + </p> + + <p> + It allows recovering the device from a bad state by booting from a trusted recovery media. + When accessed with the device in a good state, it also allows enabling developer mode. + </p> + + <div class="subsection"> + + <h2 id="recovering_bad_state">Recovering from a bad state</h2> + + <p> + When the device fails to verify the signature of a piece of the boot software or when an error occurs, + it is considered to be in a bad state and will instruct the user to reboot to recovery mode.<br /> + Recovery mode boots using only software located in write-protected memory, that is considered to be trusted and safe. + </p> + + <p> + Recovery mode then allows recovering the device by booting from a trusted recovery media, that is automatically detected when recovery mode starts. + When no external media is found or when the recovery media is invalid, instructions are shown on screen. <br /> + Trusted recovery media are external media (USB drives, SD cards, etc) that hold a kernel signed with the recovery key. + </p> + + <p> + Google provides images of such recovery media for Chrome OS (which are not advised to users as they contain proprietary software). <br /> + They are signed with Google's recovery keys, that are pre-installed on the device when it ships. + </p> + + <p> + When replacing the full flash of the device, the pre-installed keys are replaced. + When the recovery private key is available (e.g. when using self-generated keys), it can be used to sign a kernel for recovery purposes. + </p> + + </div> + + <div class="subsection"> + + <h2 id="enabling_developer_mode">Enabling developer mode</h2> + + <p> + As instructed on the recovery mode screen, developer mode can be enabled by pressing <b>Ctrl + D</b>.<br /> + Instructions to confirm enabling developer mode are then shown on screen. + </p> + + </div> + + </div> + + <div class="section"> + + <h1 id="configuring_verified_boot_parameters">Configuring verified boot parameters</h1> + + <p> + Depthcharge's behavior relies on the verified boot (vboot) reference implementation, + that can be configured with parameters stored in the verified boot non-volatile storage.<br /> + These parameters can be modified with the <b>crossystem</b> tool, that requires sufficient privileges to access the verified boot non-volatile storage. + </p> + + <p> + <b>crossystem</b> relies on <b>mosys</b>, that is used to access the verified boot non-volatile storage on some devices. + <b>crossystem</b> and <b>mosys</b> are both free software and their source code is made available by Google: <a href="https://chromium.googlesource.com/chromiumos/platform/vboot_reference/">crossystem</a>. <a href="https://chromium.googlesource.com/chromiumos/platform/mosys/">mosys</a>.<br /> + These tools are not distributed along with Libreboot yet. However, they are preinstalled on the device, with ChromeOS. + </p> + + <p> + Some of these parameters have the potential of <b>weakening the security of the device</b>. + In particular, disabling kernels signature verification, external media boot and legacy payload boot can weaken the security of the device. + </p> + + <div class="subsection"> + + <p> + The following parameters can be configured: + </p> + + <ul> + + <li> + Kernels signature verification: + <ul> + + <li> + Enabled with:<br /> + # <b>crossystem dev_boot_signed_only=1</b> + </li> + + <li> + Disabled with:<br /> + # <b>crossystem dev_boot_signed_only=0</b> + </li> + + </ul> + </li> + + <li> + External media boot: + <ul> + + <li> + Enabled with:<br /> + # <b>crossystem dev_boot_usb=1</b> + </li> + + <li> + Disabled with:<br /> + # <b>crossystem dev_boot_usb=0</b> + </li> + + </ul> + </li> + + <li> + Legacy payload boot: + <ul> + + <li> + Enabled with:<br /> + # <b>crossystem dev_boot_legacy=1</b> + </li> + + <li> + Disabled with:<br /> + # <b>crossystem dev_boot_legacy=0</b> + </li> + + </ul> + </li> + + <li> + Default boot medium: + <ul> + + <li> + Internal storage:<br /> + # <b>crossystem dev_default_boot=disk</b> + </li> + + <li> + External media:<br /> + # <b>crossystem dev_default_boot=usb</b> + </li> + + <li> + Legacy payload:<br /> + # <b>crossystem dev_default_boot=legacy</b> + </li> + + </ul> + + </ul> + + </div> + + </div> + + <div class="section"> + + <p> + Copyright &copy; 2015 Paul Kocialkowski &lt;contact@paulk.fr&gt;<br/> + Permission is granted to copy, distribute and/or modify this document + under the terms of the GNU Free Documentation License, Version 1.3 + or any later version published by the Free Software Foundation; + with no Invariant Sections, no Front-Cover Texts, and no Back-Cover Texts. + A copy of the license can be found at <a href="../gfdl-1.3.txt">../gfdl-1.3.txt</a> + </p> + + <p> + Updated versions of the license (when available) can be found at + <a href="https://www.gnu.org/licenses/licenses.html">https://www.gnu.org/licenses/licenses.html</a> + </p> + + <p> + UNLESS OTHERWISE SEPARATELY UNDERTAKEN BY THE LICENSOR, TO THE + EXTENT POSSIBLE, THE LICENSOR OFFERS THE LICENSED MATERIAL AS-IS + AND AS-AVAILABLE, AND MAKES NO REPRESENTATIONS OR WARRANTIES OF + ANY KIND CONCERNING THE LICENSED MATERIAL, WHETHER EXPRESS, + IMPLIED, STATUTORY, OR OTHER. THIS INCLUDES, WITHOUT LIMITATION, + WARRANTIES OF TITLE, MERCHANTABILITY, FITNESS FOR A PARTICULAR + PURPOSE, NON-INFRINGEMENT, ABSENCE OF LATENT OR OTHER DEFECTS, + ACCURACY, OR THE PRESENCE OR ABSENCE OF ERRORS, WHETHER OR NOT + KNOWN OR DISCOVERABLE. WHERE DISCLAIMERS OF WARRANTIES ARE NOT + ALLOWED IN FULL OR IN PART, THIS DISCLAIMER MAY NOT APPLY TO YOU. + </p> + <p> + TO THE EXTENT POSSIBLE, IN NO EVENT WILL THE LICENSOR BE LIABLE + TO YOU ON ANY LEGAL THEORY (INCLUDING, WITHOUT LIMITATION, + NEGLIGENCE) OR OTHERWISE FOR ANY DIRECT, SPECIAL, INDIRECT, + INCIDENTAL, CONSEQUENTIAL, PUNITIVE, EXEMPLARY, OR OTHER LOSSES, + COSTS, EXPENSES, OR DAMAGES ARISING OUT OF THIS PUBLIC LICENSE OR + USE OF THE LICENSED MATERIAL, EVEN IF THE LICENSOR HAS BEEN + ADVISED OF THE POSSIBILITY OF SUCH LOSSES, COSTS, EXPENSES, OR + DAMAGES. WHERE A LIMITATION OF LIABILITY IS NOT ALLOWED IN FULL OR + IN PART, THIS LIMITATION MAY NOT APPLY TO YOU. + </p> + <p> + The disclaimer of warranties and limitation of liability provided + above shall be interpreted in a manner that, to the extent + possible, most closely approximates an absolute disclaimer and + waiver of all liability. + </p> + + </div> + +</body> +</html> diff --git a/docs/future/coreboot_native_3.12_bug.tar.gz b/docs/future/coreboot_native_3.12_bug.tar.gz Binary files differ. diff --git a/docs/future/donotusethis_macbook_acpi.diff b/docs/future/donotusethis_macbook_acpi.diff @@ -0,0 +1,28 @@ +diff --git a/src/mainboard/apple/macbook21/mainboard.c b/src/mainboard/apple/macbook21/mainboard.c +index 9a025dd..a2adb76 100644 +--- a/src/mainboard/apple/macbook21/mainboard.c ++++ b/src/mainboard/apple/macbook21/mainboard.c +@@ -40,6 +40,12 @@ + extern const u32 *cim_verb_data; + extern u32 cim_verb_data_size; + ++static acpi_cstate_t cst_entries[] = { ++ { 1, 1, 1000, { 0x7f, 1, 2, { 0 }, 1, 0 } }, ++ { 2, 1, 500, { 0x01, 8, 0, { 0 }, DEFAULT_PMBASE + LV2, 0 } }, ++ { 2, 17, 250, { 0x01, 8, 0, { 0 }, DEFAULT_PMBASE + LV3, 0 } }, ++}; ++ + #if CONFIG_PCI_OPTION_ROM_RUN_YABEL || CONFIG_PCI_OPTION_ROM_RUN_REALMODE + static int int15_handler(void) + { +@@ -73,7 +79,8 @@ static int int15_handler(void) + + int get_cst_entries(acpi_cstate_t **entries) + { +- return 0; ++ *entries = cst_entries; ++ return ARRAY_SIZE(cst_entries); + } + + static void mainboard_init(device_t dev) + diff --git a/docs/future/dumps/5320_7c0000_gma.c b/docs/future/dumps/5320_7c0000_gma.c @@ -0,0 +1,519 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <bootmode.h> +#include <delay.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <pc80/mc146818rtc.h> +#include "i945.h" +#include "chip.h" +#include <edid.h> +#include <drivers/intel/gma/edid.h> +#include <drivers/intel/gma/i915.h> +#include <string.h> + +#define GDRST 0xc0 + +#define LVDS_CLOCK_A_POWERUP_ALL (3 << 8) +#define LVDS_CLOCK_B_POWERUP_ALL (3 << 4) +#define LVDS_CLOCK_BOTH_POWERUP_ALL (3 << 2) +#define DISPPLANE_BGRX888 (0x6<<26) +#define DPLLB_LVDS_P2_CLOCK_DIV_7 (1 << 24) /* i915 */ + +#define DPLL_INTEGRATED_CRI_CLK_VLV (1<<14) + +#define PGETBL_CTL 0x2020 +#define PGETBL_ENABLED 0x00000001 + +#define BASE_FREQUENCY 120000 + +#if CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT + +static int gtt_setup(unsigned int mmiobase) +{ + unsigned long PGETBL_save; + + PGETBL_save = read32(mmiobase + PGETBL_CTL) & ~PGETBL_ENABLED; + PGETBL_save |= PGETBL_ENABLED; + + PGETBL_save |= pci_read_config32(dev_find_slot(0, PCI_DEVFN(2,0)), 0x5c) & 0xfffff000; + PGETBL_save |= 2; /* set GTT to 256kb */ + + // hack!!! + PGETBL_save += 0x7c0000; // ugly hack. from 5927/3. Must calculate it properly! + /// hack!!! + + write32(mmiobase + GFX_FLSH_CNTL, 0); + + write32(mmiobase + PGETBL_CTL, PGETBL_save); + + /* verify */ +/* // old + if (read32(mmiobase + PGETBL_CTL) & PGETBL_ENABLED) { + printk(BIOS_DEBUG, "gtt_setup is enabled.\n"); +*/ + // Hack. Must do properly later: + PGETBL_save = read32(mmiobase + PGETBL_CTL); + if (PGETBL_save & PGETBL_ENABLED) { + printk(BIOS_DEBUG, "gtt_setup is enabled: GTT PGETLB_CTL register: 0x%lx\n", PGETBL_save); + // end hack + } else { + printk(BIOS_DEBUG, "gtt_setup failed!!!\n"); + return 1; + } + write32(mmiobase + GFX_FLSH_CNTL, 0); + + return 0; +} + +static int intel_gma_init(struct northbridge_intel_i945_config *conf, + unsigned int pphysbase, unsigned int piobase, + unsigned int pmmio, unsigned int pgfx) +{ + struct edid edid; + u8 edid_data[128]; + unsigned long temp; + int hpolarity, vpolarity; + u32 candp1, candn; + u32 best_delta = 0xffffffff; + u32 target_frequency; + u32 pixel_p1 = 1; + u32 pixel_n = 1; + u32 pixel_m1 = 1; + u32 pixel_m2 = 1; + u32 hactive, vactive, right_border, bottom_border; + u32 vsync, hsync, vblank, hblank, hfront_porch, vfront_porch; + u32 i, j; + + pphysbase += 0x20000; + + printk(BIOS_SPEW, + "i915lightup: graphics %p mmio %08x addrport %04x physbase %08x\n", + (void *)pgfx, pmmio, piobase, pphysbase); + + intel_gmbus_read_edid(pmmio + GMBUS0, 3, 0x50, edid_data, 128); + decode_edid(edid_data, sizeof(edid_data), &edid); + + hpolarity = (edid.phsync == '-'); + vpolarity = (edid.pvsync == '-'); + hactive = edid.x_resolution; + vactive = edid.y_resolution; + right_border = edid.hborder; + bottom_border = edid.vborder; + vblank = edid.vbl; + hblank = edid.hbl; + vsync = edid.vspw; + hsync = edid.hspw; + hfront_porch = edid.hso; + vfront_porch = edid.vso; + + for (i = 0; i < 2; i++) + for (j = 0; j < 0x100; j++) + /* R=j, G=j, B=j. */ + write32(pmmio + PALETTE(i) + 4 * j, 0x10101 * j); + + write32(pmmio + PCH_PP_CONTROL, PANEL_UNLOCK_REGS + | (read32(pmmio + PCH_PP_CONTROL) & ~PANEL_UNLOCK_MASK)); + + write32(pmmio + MI_ARB_STATE, MI_ARB_C3_LP_WRITE_ENABLE | (1 << 27)); + /* Clean registers. */ + for (i = 0; i < 0x20; i += 4) + write32(pmmio + RENDER_RING_BASE + i, 0); + for (i = 0; i < 0x20; i += 4) + write32(pmmio + FENCE_REG_965_0 + i, 0); + write32(pmmio + PP_ON_DELAYS, 0); + write32(pmmio + PP_OFF_DELAYS, 0); + + /* Disable VGA. */ + write32(pmmio + VGACNTRL, VGA_DISP_DISABLE); + + /* Disable pipes. */ + write32(pmmio + PIPECONF(0), 0); + write32(pmmio + PIPECONF(1), 0); + + /* Init PRB0. */ + write32(pmmio + HWS_PGA, 0x352d2000); + write32(pmmio + PRB0_CTL, 0); + write32(pmmio + PRB0_HEAD, 0); + write32(pmmio + PRB0_TAIL, 0); + write32(pmmio + PRB0_START, 0); + write32(pmmio + PRB0_CTL, 0x0001f001); + + write32(pmmio + D_STATE, DSTATE_PLL_D3_OFF + | DSTATE_GFX_CLOCK_GATING | DSTATE_DOT_CLOCK_GATING); + write32(pmmio + ECOSKPD, 0x00010000); + write32(pmmio + HWSTAM, 0xeffe); + write32(pmmio + PORT_HOTPLUG_EN, conf->gpu_hotplug); + write32(pmmio + INSTPM, 0x08000000 | INSTPM_AGPBUSY_DIS); + + target_frequency = conf->gpu_lvds_is_dual_channel ? edid.pixel_clock + : (2 * edid.pixel_clock); + + /* Find suitable divisors. */ + for (candp1 = 1; candp1 <= 8; candp1++) { + for (candn = 5; candn <= 10; candn++) { + u32 cur_frequency; + u32 m; /* 77 - 131. */ + u32 denom; /* 35 - 560. */ + u32 current_delta; + + denom = candn * candp1 * 7; + /* Doesnt overflow for up to + 5000000 kHz = 5 GHz. */ + m = (target_frequency * denom + + BASE_FREQUENCY / 2) / BASE_FREQUENCY; + + if (m < 77 || m > 131) + continue; + + cur_frequency = (BASE_FREQUENCY * m) / denom; + if (target_frequency > cur_frequency) + current_delta = target_frequency - cur_frequency; + else + current_delta = cur_frequency - target_frequency; + + if (best_delta > current_delta) { + best_delta = current_delta; + pixel_n = candn; + pixel_p1 = candp1; + pixel_m2 = ((m + 3) % 5) + 7; + pixel_m1 = (m - pixel_m2) / 5; + } + } + } + + if (best_delta == 0xffffffff) { + printk (BIOS_ERR, "Couldn't find GFX clock divisors\n"); + return -1; + } + + printk(BIOS_INFO, "bringing up panel at resolution %d x %d\n", + hactive, vactive); + printk(BIOS_DEBUG, "Borders %d x %d\n", right_border, bottom_border); + printk(BIOS_DEBUG, "Blank %d x %d\n", hblank, vblank); + printk(BIOS_DEBUG, "Sync %d x %d\n", hsync, vsync); + printk(BIOS_DEBUG, "Front porch %d x %d\n", hfront_porch, vfront_porch); + printk(BIOS_DEBUG, (conf->gpu_lvds_use_spread_spectrum_clock + ? "Spread spectrum clock\n" + : "DREF clock\n")); + printk(BIOS_DEBUG, (conf->gpu_lvds_is_dual_channel + ? "Dual channel\n" + : "Single channel\n")); + printk(BIOS_DEBUG, "Polarities %d, %d\n", + hpolarity, vpolarity); + printk(BIOS_DEBUG, "Pixel N=%d, M1=%d, M2=%d, P1=%d\n", + pixel_n, pixel_m1, pixel_m2, pixel_p1); + printk(BIOS_DEBUG, "Pixel clock %d kHz\n", + BASE_FREQUENCY * (5 * pixel_m1 + pixel_m2) / pixel_n + / (pixel_p1 * 7)); + + write32(pmmio + DSPCNTR(0), DISPPLANE_BGRX888 + | DISPPLANE_SEL_PIPE_B | DISPPLANE_GAMMA_ENABLE); + + mdelay(1); + write32(pmmio + PP_CONTROL, PANEL_UNLOCK_REGS + | (read32(pmmio + PP_CONTROL) & ~PANEL_UNLOCK_MASK)); + write32(pmmio + FP0(1), + ((pixel_n - 2) << 16) + | ((pixel_m1 - 2) << 8) | pixel_m2); + write32(pmmio + DPLL(1), + DPLL_VGA_MODE_DIS | + DPLL_VCO_ENABLE | DPLLB_MODE_LVDS + | (conf->gpu_lvds_is_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7 + : DPLLB_LVDS_P2_CLOCK_DIV_14) + | (conf->gpu_lvds_use_spread_spectrum_clock + ? DPLL_INTEGRATED_CLOCK_VLV | DPLL_INTEGRATED_CRI_CLK_VLV + : 0) + | (pixel_p1 << 16) + | (pixel_p1)); + mdelay(1); + write32(pmmio + DPLL(1), + DPLL_VGA_MODE_DIS | + DPLL_VCO_ENABLE | DPLLB_MODE_LVDS + | (conf->gpu_lvds_is_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7 + : DPLLB_LVDS_P2_CLOCK_DIV_14) + | ((conf->gpu_lvds_use_spread_spectrum_clock ? 3 : 0) << 13) + | (pixel_p1 << 16) + | (pixel_p1)); + mdelay(1); + write32(pmmio + HTOTAL(1), + ((hactive + right_border + hblank - 1) << 16) + | (hactive - 1)); + write32(pmmio + HBLANK(1), + ((hactive + right_border + hblank - 1) << 16) + | (hactive + right_border - 1)); + write32(pmmio + HSYNC(1), + ((hactive + right_border + hfront_porch + hsync - 1) << 16) + | (hactive + right_border + hfront_porch - 1)); + + write32(pmmio + VTOTAL(1), ((vactive + bottom_border + vblank - 1) << 16) + | (vactive - 1)); + write32(pmmio + VBLANK(1), ((vactive + bottom_border + vblank - 1) << 16) + | (vactive + bottom_border - 1)); + write32(pmmio + VSYNC(1), + (vactive + bottom_border + vfront_porch + vsync - 1) + | (vactive + bottom_border + vfront_porch - 1)); + + write32(pmmio + PIPESRC(1), ((hactive - 1) << 16) | (vactive - 1)); + + /* Disable panel fitter (we're in native resolution). */ + write32(pmmio + PF_CTL(0), 0); + write32(pmmio + PF_WIN_SZ(0), 0); + write32(pmmio + PF_WIN_POS(0), 0); + write32(pmmio + PFIT_PGM_RATIOS, 0); + write32(pmmio + PFIT_CONTROL, 0); + + mdelay(1); + + write32(pmmio + DSPSIZE(0), (hactive - 1) | ((vactive - 1) << 16)); + write32(pmmio + DSPPOS(0), 0); + + /* Backlight init. */ + write32(pmmio + FW_BLC_SELF, FW_BLC_SELF_EN_MASK); + write32(pmmio + FW_BLC, 0x011d011a); + write32(pmmio + FW_BLC2, 0x00000102); + write32(pmmio + FW_BLC_SELF, FW_BLC_SELF_EN_MASK); + write32(pmmio + FW_BLC_SELF, 0x0001003f); + write32(pmmio + FW_BLC, 0x011d0109); + write32(pmmio + FW_BLC2, 0x00000102); + write32(pmmio + FW_BLC_SELF, FW_BLC_SELF_EN_MASK); + write32(pmmio + BLC_PWM_CTL, conf->gpu_backlight); + + edid.bytes_per_line = (edid.bytes_per_line + 63) & ~63; + write32(pmmio + DSPADDR(0), 0); + write32(pmmio + DSPSURF(0), 0); + write32(pmmio + DSPSTRIDE(0), edid.bytes_per_line); + write32(pmmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE | DISPPLANE_BGRX888 + | DISPPLANE_SEL_PIPE_B | DISPPLANE_GAMMA_ENABLE); + mdelay(1); + + write32(pmmio + PIPECONF(1), PIPECONF_ENABLE); + write32(pmmio + LVDS, LVDS_ON + | (hpolarity << 20) | (vpolarity << 21) + | (conf->gpu_lvds_is_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL + | LVDS_CLOCK_BOTH_POWERUP_ALL : 0) + | LVDS_CLOCK_A_POWERUP_ALL + | LVDS_PIPE(1)); + + write32(pmmio + PP_CONTROL, PANEL_UNLOCK_REGS | PANEL_POWER_OFF); + write32(pmmio + PP_CONTROL, PANEL_UNLOCK_REGS | PANEL_POWER_RESET); + mdelay(1); + write32(pmmio + PP_CONTROL, PANEL_UNLOCK_REGS + | PANEL_POWER_ON | PANEL_POWER_RESET); + + printk (BIOS_DEBUG, "waiting for panel powerup\n"); + while (1) { + u32 reg32; + reg32 = read32(pmmio + PP_STATUS); + if ((reg32 & PP_SEQUENCE_MASK) == PP_SEQUENCE_NONE) + break; + } + printk (BIOS_DEBUG, "panel powered up\n"); + + write32(pmmio + PP_CONTROL, PANEL_POWER_ON | PANEL_POWER_RESET); + + /* Clear interrupts. */ + write32(pmmio + DEIIR, 0xffffffff); + write32(pmmio + SDEIIR, 0xffffffff); + write32(pmmio + IIR, 0xffffffff); + write32(pmmio + IMR, 0xffffffff); + write32(pmmio + EIR, 0xffffffff); + + /* GTT is the Global Translation Table for the graphics pipeline. + * It is used to translate graphics addresses to physical + * memory addresses. As in the CPU, GTTs map 4K pages. + * There are 32 bits per pixel, or 4 bytes, + * which means 1024 pixels per page. + * There are 4250 GTTs on Link: + * 2650 (X) * 1700 (Y) pixels / 1024 pixels per page. + * The setgtt function adds a further bit of flexibility: + * it allows you to set a range (the first two parameters) to point + * to a physical address (third parameter);the physical address is + * incremented by a count (fourth parameter) for each GTT in the + * range. + * Why do it this way? For ultrafast startup, + * we can point all the GTT entries to point to one page, + * and set that page to 0s: + * memset(physbase, 0, 4096); + * setgtt(0, 4250, physbase, 0); + * this takes about 2 ms, and is a win because zeroing + * the page takes a up to 200 ms. We will be exploiting this + * trick in a later rev of this code. + * This call sets the GTT to point to a linear range of pages + * starting at physbase. + */ + + if (gtt_setup(pmmio)) { + printk(BIOS_ERR, "ERROR: GTT Setup Failed!!!\n"); + return 0; + } + + /* Setup GTT. */ + for (i = 0; i < 0x2000; i++) + { + outl((i << 2) | 1, piobase); + outl(pphysbase + (i << 12) + 1, piobase + 4); + } + + temp = read32(pmmio + PGETBL_CTL); + printk(BIOS_INFO, "GTT PGETBL_CTL register: 0x%lx\n", temp); + + if (temp & 1) + printk(BIOS_INFO, "GTT Enabled\n"); + else + printk(BIOS_ERR, "ERROR: GTT is still Disabled!!!\n"); + + printk(BIOS_SPEW, "memset %p to 0x00 for %d bytes\n", + (void *)pgfx, hactive * vactive * 4); + memset((void *)pgfx, 0x00, hactive * vactive * 4); + + set_vbe_mode_info_valid(&edid, pgfx); + + return 0; +} +#endif + +static void gma_func0_init(struct device *dev) +{ + u32 reg32; + + /* Unconditionally reset graphics */ + pci_write_config8(dev, GDRST, 1); + udelay(50); + pci_write_config8(dev, GDRST, 0); + /* wait for device to finish */ + while (pci_read_config8(dev, GDRST) & 1) { }; + + /* IGD needs to be Bus Master */ + reg32 = pci_read_config32(dev, PCI_COMMAND); + pci_write_config32(dev, PCI_COMMAND, reg32 | PCI_COMMAND_MASTER + | PCI_COMMAND_IO | PCI_COMMAND_MEMORY); + +#if !CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT + /* PCI Init, will run VBIOS */ + pci_dev_init(dev); +#endif + + +#if CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT + /* This should probably run before post VBIOS init. */ + printk(BIOS_SPEW, "Initializing VGA without OPROM.\n"); + u32 iobase, mmiobase, graphics_base; + struct northbridge_intel_i945_config *conf = dev->chip_info; + + iobase = dev->resource_list[1].base; + mmiobase = dev->resource_list[0].base; + graphics_base = dev->resource_list[2].base; + + printk(BIOS_SPEW, "GMADR=0x%08x GTTADR=0x%08x\n", + pci_read_config32(dev, 0x18), + pci_read_config32(dev, 0x1c) + ); + + int err; + err = intel_gma_init(conf, pci_read_config32(dev, 0x5c) & ~0xf, + iobase, mmiobase, graphics_base); + if (err == 0) + gfx_set_init_done(1); +#endif +} + +/* This doesn't reclaim stolen UMA memory, but IGD could still + be reenabled later. */ +static void gma_func0_disable(struct device *dev) +{ + struct device *dev_host = dev_find_slot(0, PCI_DEVFN(0x0, 0)); + + pci_write_config16(dev, GCFC, 0xa00); + pci_write_config16(dev_host, GGC, (1 << 1)); + + unsigned int reg32 = pci_read_config32(dev_host, DEVEN); + reg32 &= ~(DEVEN_D2F0 | DEVEN_D2F1); + pci_write_config32(dev_host, DEVEN, reg32); + + dev->enabled = 0; +} + +static void gma_func1_init(struct device *dev) +{ + u32 reg32; + u8 val; + + /* IGD needs to be Bus Master, also enable IO accesss */ + reg32 = pci_read_config32(dev, PCI_COMMAND); + pci_write_config32(dev, PCI_COMMAND, reg32 | + PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO); + + if (get_option(&val, "tft_brightness") == CB_SUCCESS) + pci_write_config8(dev, 0xf4, val); + else + pci_write_config8(dev, 0xf4, 0xff); +} + +static void gma_set_subsystem(device_t dev, unsigned vendor, unsigned device) +{ + if (!vendor || !device) { + pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, + pci_read_config32(dev, PCI_VENDOR_ID)); + } else { + pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, + ((device & 0xffff) << 16) | (vendor & 0xffff)); + } +} + +static struct pci_operations gma_pci_ops = { + .set_subsystem = gma_set_subsystem, +}; + +static struct device_operations gma_func0_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = gma_func0_init, + .scan_bus = 0, + .enable = 0, + .disable = gma_func0_disable, + .ops_pci = &gma_pci_ops, +}; + + +static struct device_operations gma_func1_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = gma_func1_init, + .scan_bus = 0, + .enable = 0, + .ops_pci = &gma_pci_ops, +}; + +static const struct pci_driver i945_gma_func0_driver __pci_driver = { + .ops = &gma_func0_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = 0x27a2, +}; + +static const struct pci_driver i945_gma_func1_driver __pci_driver = { + .ops = &gma_func1_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = 0x27a6, +}; diff --git a/docs/future/dumps/5885_logs.tar.gz b/docs/future/dumps/5885_logs.tar.gz Binary files differ. diff --git a/docs/future/dumps/5885_logs_2.tar.gz b/docs/future/dumps/5885_logs_2.tar.gz Binary files differ. diff --git a/docs/future/dumps/5927_2.tar.gz b/docs/future/dumps/5927_2.tar.gz Binary files differ. diff --git a/docs/future/dumps/5927_3.tar.gz b/docs/future/dumps/5927_3.tar.gz Binary files differ. diff --git a/docs/future/dumps/5927_5.tar.gz b/docs/future/dumps/5927_5.tar.gz Binary files differ. diff --git a/docs/future/dumps/5927_6.tar.gz b/docs/future/dumps/5927_6.tar.gz Binary files differ. diff --git a/docs/future/dumps/5927_7.tar.gz b/docs/future/dumps/5927_7.tar.gz Binary files differ. diff --git a/docs/future/dumps/5927_cbmemc b/docs/future/dumps/5927_cbmemc @@ -0,0 +1,1442 @@ + + +coreboot-4.0-6196-g1aa8cbd-7BETC7WW (2.08 ) Tue Jun 3 22:16:33 BST 2014 starting... + +Mobile Intel(R) 82945GM/GME Express Chipset +(G)MCH capable of up to FSB 800 MHz +(G)MCH capable of up to DDR2-667 +Setting up static southbridge registers... GPIOS... done. +Disabling Watchdog reboot... done. +Setting up static northbridge registers... done. +Waiting for MCHBAR to come up...ok +PM1_CNT: 00001c00 +SMBus controller enabled. +Setting up RAM controller. +This mainboard supports Dual Channel Operation. +DDR II Channel 0 Socket 0: x16DS +DDR II Channel 1 Socket 0: x8DDS +Memory will be driven at 667MHz with CAS=5 clocks +tRAS = 15 cycles +tRP = 5 cycles +tRCD = 5 cycles +Refresh: 7.8us +tWR = 5 cycles +DIMM 0 side 0 = 512 MB +DIMM 0 side 1 = 512 MB +DIMM 2 side 0 = 1024 MB +DIMM 2 side 1 = 1024 MB +tRFC = 43 cycles +Setting Graphics Frequency... +FSB: 667 MHz Voltage: 1.05V Render: 250Mhz Display: 200MHz +Setting Memory Frequency... CLKCFG=0x00010023, CLKCFG=0x00010043, ok +Setting mode of operation for memory channels...Dual Channel Assymetric. +Programming Clock Crossing...MEM=667 FSB=667... ok +Setting RAM size... +C0DRB = 0x20202010 +C1DRB = 0x60606040 +TOLUD = 0x00c0 +Setting row attributes... +C0DRA = 0x0033 +C1DRA = 0x0033 +DIMM0 has 8 banks. +DIMM2 has 8 banks. +one dimm per channel config.. +Initializing System Memory IO... +Programming Dual Channel RCOMP +Table Index: 3 +Programming DLL Timings... +Enabling System Memory IO... +jedec enable sequence: bank 0 +jedec enable sequence: bank 1 +bankaddr from bank size of rank 0 +jedec enable sequence: bank 4 +bankaddr from bank size of rank 1 +jedec enable sequence: bank 5 +bankaddr from bank size of rank 4 +receive_enable_autoconfig() for channel 0 + find_strobes_low() + set_receive_enable() medium=0x3, coarse=0x5 + set_receive_enable() medium=0x1, coarse=0x5 + find_strobes_edge() + set_receive_enable() medium=0x1, coarse=0x5 + set_receive_enable() medium=0x3, coarse=0x5 + set_receive_enable() medium=0x1, coarse=0x5 + add_quarter_clock() mediumcoarse=15 fine=f3 + set_receive_enable() medium=0x3, coarse=0x5 + find_preamble() + set_receive_enable() medium=0x3, coarse=0x4 + set_receive_enable() medium=0x3, coarse=0x3 + add_quarter_clock() mediumcoarse=0f fine=73 + normalize() + set_receive_enable() medium=0x0, coarse=0x4 +receive_enable_autoconfig() for channel 1 + find_strobes_low() + set_receive_enable() medium=0x3, coarse=0x5 + set_receive_enable() medium=0x1, coarse=0x5 + find_strobes_edge() + set_receive_enable() medium=0x1, coarse=0x5 + add_quarter_clock() mediumcoarse=15 fine=c5 + set_receive_enable() medium=0x3, coarse=0x5 + find_preamble() + set_receive_enable() medium=0x3, coarse=0x4 + set_receive_enable() medium=0x3, coarse=0x3 + add_quarter_clock() mediumcoarse=0f fine=45 + normalize() + set_receive_enable() medium=0x0, coarse=0x4 +RAM initialization finished. +Setting up Egress Port RCRB +Loading p + +*** Log truncated, 497 characters dropped. *** + +Adding CBMEM entry as no. 3 +Trying CBFS ramstage loader. +CBFS: loading stage fallback/ramstage @ 0x100000 (417848 bytes), entry @ 0x100000 +coreboot-4.0-6196-g1aa8cbd-7BETC7WW (2.08 ) Tue Jun 3 22:16:33 BST 2014 booting... +BS: Entering BS_PRE_DEVICE state. +BS: Exiting BS_PRE_DEVICE state. +BS: BS_PRE_DEVICE times (us): entry 0 run 2975 exit 0 +BS: Entering BS_DEV_INIT_CHIPS state. +BS: Exiting BS_DEV_INIT_CHIPS state. +BS: BS_DEV_INIT_CHIPS times (us): entry 0 run 3324 exit 0 +BS: Entering BS_DEV_ENUMERATE state. +Enumerating buses... +Show all devs...Before device enumeration. +Root Device: enabled 1 +CPU_CLUSTER: 0: enabled 1 +APIC: 00: enabled 1 +DOMAIN: 0000: enabled 1 +PCI: 00:00.0: enabled 1 +PCI: 00:02.0: enabled 1 +PCI: 00:02.1: enabled 1 +PCI: 00:1b.0: enabled 1 +PCI: 00:1c.0: enabled 1 +PCI: 00:1c.1: enabled 1 +PCI: 00:1d.0: enabled 1 +PCI: 00:1d.1: enabled 1 +PCI: 00:1d.2: enabled 1 +PCI: 00:1d.3: enabled 1 +PCI: 00:1d.7: enabled 1 +PCI: 00:1f.0: enabled 1 +PNP: 00ff.1: enabled 1 +PNP: 00ff.2: enabled 1 +PNP: 164e.2: enabled 1 +PNP: 164e.3: enabled 0 +PNP: 164e.7: enabled 1 +PNP: 164e.19: enabled 1 +PNP: 002e.0: enabled 0 +PNP: 002e.1: enabled 1 +PNP: 002e.2: enabled 0 +PNP: 002e.3: enabled 1 +PNP: 002e.7: enabled 1 +PNP: 002e.a: enabled 0 +PCI: 00:1f.1: enabled 1 +PCI: 00:1f.2: enabled 1 +PCI: 00:1f.3: enabled 1 +I2C: 00:69: enabled 1 +I2C: 00:54: enabled 1 +I2C: 00:55: enabled 1 +I2C: 00:56: enabled 1 +I2C: 00:57: enabled 1 +I2C: 00:5c: enabled 1 +I2C: 00:5d: enabled 1 +I2C: 00:5e: enabled 1 +I2C: 00:5f: enabled 1 +Compare with tree... +Root Device: enabled 1 + CPU_CLUSTER: 0: enabled 1 + APIC: 00: enabled 1 + DOMAIN: 0000: enabled 1 + PCI: 00:00.0: enabled 1 + PCI: 00:02.0: enabled 1 + PCI: 00:02.1: enabled 1 + PCI: 00:1b.0: enabled 1 + PCI: 00:1c.0: enabled 1 + PCI: 00:1c.1: enabled 1 + PCI: 00:1d.0: enabled 1 + PCI: 00:1d.1: enabled 1 + PCI: 00:1d.2: enabled 1 + PCI: 00:1d.3: enabled 1 + PCI: 00:1d.7: enabled 1 + PCI: 00:1f.0: enabled 1 + PNP: 00ff.1: enabled 1 + PNP: 00ff.2: enabled 1 + PNP: 164e.2: enabled 1 + PNP: 164e.3: enabled 0 + PNP: 164e.7: enabled 1 + PNP: 164e.19: enabled 1 + PNP: 002e.0: enabled 0 + PNP: 002e.1: enabled 1 + PNP: 002e.2: enabled 0 + PNP: 002e.3: enabled 1 + PNP: 002e.7: enabled 1 + PNP: 002e.a: enabled 0 + PCI: 00:1f.1: enabled 1 + PCI: 00:1f.2: enabled 1 + PCI: 00:1f.3: enabled 1 + I2C: 00:69: enabled 1 + I2C: 00:54: enabled 1 + I2C: 00:55: enabled 1 + I2C: 00:56: enabled 1 + I2C: 00:57: enabled 1 + I2C: 00:5c: enabled 1 + I2C: 00:5d: enabled 1 + I2C: 00:5e: enabled 1 + I2C: 00:5f: enabled 1 +scan_static_bus for Root Device +CPU_CLUSTER: 0 enabled +DOMAIN: 0000 enabled +DOMAIN: 0000 scanning... +PCI: pci_scan_bus for bus 00 +PCI: 00:00.0 [8086/27a0] ops +PCI: 00:00.0 [8086/27a0] enabled +PCI: 00:02.0 [8086/27a2] ops +PCI: 00:02.0 [8086/27a2] enabled +PCI: 00:02.1 [8086/27a6] ops +PCI: 00:02.1 [8086/27a6] enabled +PCI: 00:1b.0 [8086/27d8] ops +PCI: 00:1b.0 [8086/27d8] enabled +PCI: 00:1c.0 [8086/0000] bus ops +PCI: 00:1c.0 [8086/27d0] enabled +PCI: 00:1c.1 [8086/0000] bus ops +PCI: 00:1c.1 [8086/27d2] enabled +PCI: 00:1c.2 [8086/0000] bus ops +PCI: 00:1c.2 [8086/27d4] enabled +PCI: 00:1c.3 [8086/0000] bus ops +PCI: 00:1c.3 [8086/27d6] enabled +PCI: 00:1d.0 [8086/27c8] ops +PCI: 00:1d.0 [8086/27c8] enabled +PCI: 00:1d.1 [8086/27c9] ops +PCI: 00:1d.1 [8086/27c9] enabled +PCI: 00:1d.2 [8086/27ca] ops +PCI: 00:1d.2 [8086/27ca] enabled +PCI: 00:1d.3 [8086/27cb] ops +PCI: 00:1d.3 [8086/27cb] enabled +PCI: 00:1d.7 [8086/27cc] ops +PCI: 00:1d.7 [8086/27cc] enabled +PCI: 00:1e.0 [8086/2448] bus ops +PCI: 00:1e.0 [8086/2448] enabled +PCI: 00:1f.0 [8086/27b9] bus ops +PCI: 00:1f.0 [8086/27b9] enabled +PCI: 00:1f.1 [8086/27df] ops +PCI: 00:1f.1 [8086/27df] enabled +PCI: 00:1f.2 [8086/0000] ops +PCI: 00:1f.2 [8086/27c4] enabled +PCI: 00:1f.3 [8086/27da] bus ops +PCI: 00:1f.3 [8086/27da] enabled +do_pci_scan_bridge for PCI: 00:1c.0 +PCI: pci_scan_bus for bus 01 +PCI: 01:00.0 [8086/109a] enabled +PCI: pci_scan_bus returning with max=001 +do_pci_scan_bridge returns max 1 +do_pci_scan_bridge for PCI: 00:1c.1 +PCI: pci_scan_bus for bus 02 +PCI: 02:00.0 [168c/002b] enabled +PCI: pci_scan_bus returning with max=002 +do_pci_scan_bridge returns max 2 +do_pci_scan_bridge for PCI: 00:1c.2 +PCI: pci_scan_bus for bus 03 +PCI: pci_scan_bus returning with max=003 +do_pci_scan_bridge returns max 3 +do_pci_scan_bridge for PCI: 00:1c.3 +PCI: pci_scan_bus for bus 04 +PCI: pci_scan_bus returning with max=004 +do_pci_scan_bridge returns max 4 +do_pci_scan_bridge for PCI: 00:1e.0 +PCI: pci_scan_bus for bus 05 +PCI: 05:00.0 [1180/0476] bus ops +PCI: 05:00.0 [1180/0476] enabled +PCI: 05:00.1 [1180/0552] enabled +PCI: 05:00.2 [1180/0822] enabled +PCI: 05:00.3 [1180/0843] enabled +do_pci_scan_bridge for PCI: 05:00.0 +PCI: pci_scan_bus for bus 06 +PCI: pci_scan_bus returning with max=006 +do_pci_scan_bridge returns max 6 +PCI: pci_scan_bus returning with max=006 +do_pci_scan_bridge returns max 6 +scan_static_bus for PCI: 00:1f.0 +WARNING: No CMOS option 'touchpad'. +PNP: 00ff.1 enabled +recv_ec_data: 0x37 +recv_ec_data: 0x42 +recv_ec_data: 0x48 +recv_ec_data: 0x54 +recv_ec_data: 0x33 +recv_ec_data: 0x37 +recv_ec_data: 0x57 +recv_ec_data: 0x57 +recv_ec_data: 0x04 +recv_ec_data: 0x03 +recv_ec_data: 0x00 +recv_ec_data: 0x11 +EC Firmware ID 7BHT37WW-3.4, Version 0.01B +recv_ec_data: 0x00 +recv_ec_data: 0x10 +recv_ec_data: 0x20 +recv_ec_data: 0x30 +recv_ec_data: 0x00 +recv_ec_data: 0xa6 +recv_ec_data: 0x01 +recv_ec_data: 0x30 +PNP: 00ff.2 enabled +PNP: 164e.2 enabled +PNP: 164e.3 disabled +PNP: 164e.7 enabled +PNP: 164e.19 enabled +PNP: 002e.0 disabled +PNP: 002e.1 enabled +PNP: 002e.2 disabled +PNP: 002e.3 enabled +PNP: 002e.7 enabled +PNP: 002e.a disabled +scan_static_bus for PCI: 00:1f.0 done +scan_static_bus for PCI: 00:1f.3 +smbus: PCI: 00:1f.3[0]->I2C: 01:69 enabled +smbus: PCI: 00:1f.3[0]->I2C: 01:54 enabled +smbus: PCI: 00:1f.3[0]->I2C: 01:55 enabled +smbus: PCI: 00:1f.3[0]->I2C: 01:56 enabled +smbus: PCI: 00:1f.3[0]->I2C: 01:57 enabled +smbus: PCI: 00:1f.3[0]->I2C: 01:5c enabled +smbus: PCI: 00:1f.3[0]->I2C: 01:5d enabled +smbus: PCI: 00:1f.3[0]->I2C: 01:5e enabled +smbus: PCI: 00:1f.3[0]->I2C: 01:5f enabled +scan_static_bus for PCI: 00:1f.3 done +PCI: pci_scan_bus returning with max=006 +scan_static_bus for Root Device done +done +BS: Exiting BS_DEV_ENUMERATE state. +BS: BS_DEV_ENUMERATE times (us): entry 0 run 529332 exit 0 +BS: Entering BS_DEV_RESOURCES state. +found VGA at PCI: 00:02.0 +Setting up VGA for PCI: 00:02.0 +Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000 +Setting PCI_BRIDGE_CTL_VGA for bridge Root Device +Allocating resources... +Reading resources... +Root Device read_resources bus 0 link: 0 +CPU_CLUSTER: 0 read_resources bus 0 link: 0 +APIC: 00 missing read_resources +CPU_CLUSTER: 0 read_resources bus 0 link: 0 done +DOMAIN: 0000 read_resources bus 0 link: 0 +Adding PCIe enhanced config space BAR 0xf0000000-0xf4000000. +PCI: 00:1c.0 read_resources bus 1 link: 0 +PCI: 00:1c.0 read_resources bus 1 link: 0 done +PCI: 00:1c.1 read_resources bus 2 link: 0 +PCI: 00:1c.1 read_resources bus 2 link: 0 done +PCI: 00:1c.2 read_resources bus 3 link: 0 +PCI: 00:1c.2 read_resources bus 3 link: 0 done +PCI: 00:1c.3 read_resources bus 4 link: 0 +PCI: 00:1c.3 read_resources bus 4 link: 0 done +PCI: 00:1e.0 read_resources bus 5 link: 0 +PCI: 05:00.0 read_resources bus 6 link: 0 +PCI: 05:00.0 read_resources bus 6 link: 0 done +PCI: 00:1e.0 read_resources bus 5 link: 0 done +PCI: 00:1f.0 read_resources bus 0 link: 0 +PNP: 00ff.1 missing read_resources +PNP: 00ff.2 missing read_resources +PCI: 00:1f.0 read_resources bus 0 link: 0 done +PCI: 00:1f.3 read_resources bus 1 link: 0 +PCI: 00:1f.3 read_resources bus 1 link: 0 done +DOMAIN: 0000 read_resources bus 0 link: 0 done +Root Device read_resources bus 0 link: 0 done +Done reading resources. +Show resources in subtree (Root Device)...After reading. + Root Device child on link 0 CPU_CLUSTER: 0 + CPU_CLUSTER: 0 child on link 0 APIC: 00 + APIC: 00 + DOMAIN: 0000 child on link 0 PCI: 00:00.0 + DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000 + DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffffffff flags 40040200 index 10000100 + PCI: 00:00.0 + PCI: 00:00.0 resource base f0000000 size 4000000 align 0 gran 0 limit 0 flags e0000200 index cf + PCI: 00:02.0 + PCI: 00:02.0 resource base 0 size 80000 align 19 gran 19 limit ffffffff flags 200 index 10 + PCI: 00:02.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 14 + PCI: 00:02.0 resource base 0 size 10000000 align 28 gran 28 limit ffffffff flags 1200 index 18 + PCI: 00:02.0 resource base 0 size 40000 align 18 gran 18 limit ffffffff flags 200 index 1c + PCI: 00:02.1 + PCI: 00:02.1 resource base 0 size 80000 align 19 gran 19 limit ffffffff flags 200 index 10 + PCI: 00:1b.0 + PCI: 00:1b.0 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10 + PCI: 00:1c.0 child on link 0 PCI: 01:00.0 + PCI: 00:1c.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c + PCI: 00:1c.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 + PCI: 00:1c.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 + PCI: 01:00.0 + PCI: 01:00.0 resource base 0 size 20000 align 17 gran 17 limit ffffffff flags 200 index 10 + PCI: 01:00.0 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 18 + PCI: 00:1c.1 child on link 0 PCI: 02:00.0 + PCI: 00:1c.1 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c + PCI: 00:1c.1 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 + PCI: 00:1c.1 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 + PCI: 02:00.0 + PCI: 02:00.0 resource base 0 size 10000 align 16 gran 16 limit ffffffffffffffff flags 201 index 10 + PCI: 00:1c.2 + PCI: 00:1c.2 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c + PCI: 00:1c.2 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 + PCI: 00:1c.2 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 + PCI: 00:1c.3 + PCI: 00:1c.3 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c + PCI: 00:1c.3 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 + PCI: 00:1c.3 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 + PCI: 00:1d.0 + PCI: 00:1d.0 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 20 + PCI: 00:1d.1 + PCI: 00:1d.1 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 20 + PCI: 00:1d.2 + PCI: 00:1d.2 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 20 + PCI: 00:1d.3 + PCI: 00:1d.3 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 20 + PCI: 00:1d.7 + PCI: 00:1d.7 resource base 0 size 400 align 10 gran 10 limit ffffffff flags 200 index 10 + PCI: 00:1e.0 child on link 0 PCI: 05:00.0 + PCI: 00:1e.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c + PCI: 00:1e.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 + PCI: 00:1e.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 + PCI: 05:00.0 + PCI: 05:00.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10 + PCI: 05:00.0 resource base 0 size 1000 align 2 gran 2 limit ffffffff flags 100 index 2c + PCI: 05:00.0 resource base 0 size 1000 align 2 gran 2 limit ffffffff flags 100 index 34 + PCI: 05:00.0 resource base 0 size 2000000 align 12 gran 12 limit ffffffff flags 1200 index 1c + PCI: 05:00.0 resource base 0 size 2000000 align 12 gran 12 limit ffffffff flags 200 index 24 + PCI: 05:00.1 + PCI: 05:00.1 resource base 0 size 800 align 11 gran 11 limit ffffffff flags 200 index 10 + PCI: 05:00.2 + PCI: 05:00.2 resource base 0 size 100 align 8 gran 8 limit ffffffff flags 200 index 10 + PCI: 05:00.3 + PCI: 05:00.3 resource base 0 size 100 align 8 gran 8 limit ffffffff flags 200 index 10 + PCI: 00:1f.0 child on link 0 PNP: 00ff.1 + PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000 + PCI: 00:1f.0 resource base ff800000 size 800000 align 0 gran 0 limit 0 flags c0040200 index 10000100 + PCI: 00:1f.0 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3 + PNP: 00ff.1 + PNP: 00ff.1 resource base 15e0 size 10 align 5 gran 5 limit 0 flags 80000100 index 77 + PNP: 00ff.2 + PNP: 00ff.2 resource base 62 size 0 align 0 gran 0 limit 0 flags c0000100 index 60 + PNP: 00ff.2 resource base 66 size 0 align 0 gran 0 limit 0 flags c0000100 index 62 + PNP: 00ff.2 resource base 1600 size 0 align 0 gran 0 limit 0 flags c0000100 index 64 + PNP: 00ff.2 resource base 1604 size 0 align 0 gran 0 limit 0 flags c0000100 index 66 + PNP: 164e.2 + PNP: 164e.2 resource base 2f8 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60 + PNP: 164e.2 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 + PNP: 164e.2 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74 + PNP: 164e.2 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 75 + PNP: 164e.3 + PNP: 164e.3 resource base 3f8 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60 + PNP: 164e.3 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 + PNP: 164e.7 + PNP: 164e.7 resource base 1680 size 10 align 4 gran 4 limit ffff flags c0000100 index 60 + PNP: 164e.7 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 + PNP: 164e.19 + PNP: 164e.19 resource base 164c size 2 align 1 gran 1 limit ffff flags c0000100 index 60 + PNP: 164e.19 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 + PNP: 002e.0 + PNP: 002e.0 resource base 0 size 8 align 3 gran 3 limit 7ff flags 100 index 60 + PNP: 002e.0 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 + PNP: 002e.0 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74 + PNP: 002e.1 + PNP: 002e.1 resource base 3bc size 400 align 10 gran 10 limit 7ff flags c0000100 index 60 + PNP: 002e.1 resource base 7 size 1 align 0 gran 0 limit 0 flags c0000400 index 70 + PNP: 002e.1 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74 + PNP: 002e.2 + PNP: 002e.2 resource base 2f8 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60 + PNP: 002e.2 resource base 4 size 1 align 0 gran 0 limit 0 flags c0000400 index 70 + PNP: 002e.2 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74 + PNP: 002e.2 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 75 + PNP: 002e.3 + PNP: 002e.3 resource base 3f8 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60 + PNP: 002e.3 resource base 4 size 1 align 0 gran 0 limit 0 flags c0000400 index 70 + PNP: 002e.7 + PNP: 002e.7 resource base 1620 size 8 align 3 gran 3 limit ffff flags c0000100 index 60 + PNP: 002e.7 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 + PNP: 002e.a + PNP: 002e.a resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 60 + PNP: 002e.a resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 + PCI: 00:1f.1 + PCI: 00:1f.1 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 10 + PCI: 00:1f.1 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 14 + PCI: 00:1f.1 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 18 + PCI: 00:1f.1 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 1c + PCI: 00:1f.1 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 index 20 + PCI: 00:1f.2 + PCI: 00:1f.2 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 10 + PCI: 00:1f.2 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 14 + PCI: 00:1f.2 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 18 + PCI: 00:1f.2 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 1c + PCI: 00:1f.2 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 index 20 + PCI: 00:1f.2 resource base 0 size 400 align 10 gran 10 limit ffffffff flags 200 index 24 + PCI: 00:1f.3 child on link 0 I2C: 01:69 + PCI: 00:1f.3 resource base 400 size 20 align 0 gran 0 limit 41f flags f0000100 index 20 + I2C: 01:69 + I2C: 01:54 + I2C: 01:55 + I2C: 01:56 + I2C: 01:57 + I2C: 01:5c + I2C: 01:5d + I2C: 01:5e + I2C: 01:5f +DOMAIN: 0000 compute_resources_io: base: 0 size: 0 align: 0 gran: 0 limit: ffff +PCI: 00:1c.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff +PCI: 01:00.0 18 * [0x0 - 0x1f] io +PCI: 00:1c.0 compute_resources_io: base: 20 size: 1000 align: 12 gran: 12 limit: ffff done +PCI: 00:1c.1 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff +PCI: 00:1c.1 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done +PCI: 00:1c.2 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff +PCI: 00:1c.2 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done +PCI: 00:1c.3 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff +PCI: 00:1c.3 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done +PCI: 00:1e.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff +PCI: 05:00.0 2c * [0x0 - 0xfff] io +PCI: 05:00.0 34 * [0x1000 - 0x1fff] io +PCI: 00:1e.0 compute_resources_io: base: 2000 size: 2000 align: 12 gran: 12 limit: ffff done +PCI: 00:1e.0 1c * [0x0 - 0x1fff] io +PCI: 00:1c.0 1c * [0x2000 - 0x2fff] io +PCI: 00:1d.0 20 * [0x3000 - 0x301f] io +PCI: 00:1d.1 20 * [0x3020 - 0x303f] io +PCI: 00:1d.2 20 * [0x3040 - 0x305f] io +PCI: 00:1d.3 20 * [0x3060 - 0x307f] io +PCI: 00:1f.1 20 * [0x3080 - 0x308f] io +PCI: 00:1f.2 20 * [0x3090 - 0x309f] io +PCI: 00:02.0 14 * [0x30a0 - 0x30a7] io +PCI: 00:1f.1 10 * [0x30a8 - 0x30af] io +PCI: 00:1f.1 18 * [0x30b0 - 0x30b7] io +PCI: 00:1f.2 10 * [0x30b8 - 0x30bf] io +PCI: 00:1f.2 18 * [0x30c0 - 0x30c7] io +PCI: 00:1f.1 14 * [0x30c8 - 0x30cb] io +PCI: 00:1f.1 1c * [0x30cc - 0x30cf] io +PCI: 00:1f.2 14 * [0x30d0 - 0x30d3] io +PCI: 00:1f.2 1c * [0x30d4 - 0x30d7] io +DOMAIN: 0000 compute_resources_io: base: 30d8 size: 30d8 align: 12 gran: 0 limit: ffff done +DOMAIN: 0000 compute_resources_mem: base: 0 size: 0 align: 0 gran: 0 limit: ffffffff +PCI: 00:1c.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff +PCI: 00:1c.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done +PCI: 00:1c.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff +PCI: 01:00.0 10 * [0x0 - 0x1ffff] mem +PCI: 00:1c.0 compute_resources_mem: base: 20000 size: 100000 align: 20 gran: 20 limit: ffffffff done +PCI: 00:1c.1 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff +PCI: 00:1c.1 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done +PCI: 00:1c.1 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff +PCI: 02:00.0 10 * [0x0 - 0xffff] mem +PCI: 00:1c.1 compute_resources_mem: base: 10000 size: 100000 align: 20 gran: 20 limit: ffffffff done +PCI: 00:1c.2 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff +PCI: 00:1c.2 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done +PCI: 00:1c.2 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff +PCI: 00:1c.2 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done +PCI: 00:1c.3 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff +PCI: 00:1c.3 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done +PCI: 00:1c.3 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff +PCI: 00:1c.3 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done +PCI: 00:1e.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff +PCI: 05:00.0 1c * [0x0 - 0x1ffffff] prefmem +PCI: 00:1e.0 compute_resources_prefmem: base: 2000000 size: 2000000 align: 20 gran: 20 limit: ffffffff done +PCI: 00:1e.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff +PCI: 05:00.0 24 * [0x0 - 0x1ffffff] mem +PCI: 05:00.0 10 * [0x2000000 - 0x2000fff] mem +PCI: 05:00.1 10 * [0x2001000 - 0x20017ff] mem +PCI: 05:00.2 10 * [0x2001800 - 0x20018ff] mem +PCI: 05:00.3 10 * [0x2001900 - 0x20019ff] mem +PCI: 00:1e.0 compute_resources_mem: base: 2001a00 size: 2100000 align: 20 gran: 20 limit: ffffffff done +PCI: 00:02.0 18 * [0x0 - 0xfffffff] prefmem +PCI: 00:1e.0 20 * [0x10000000 - 0x120fffff] mem +PCI: 00:1e.0 24 * [0x12100000 - 0x140fffff] prefmem +PCI: 00:1c.0 20 * [0x14100000 - 0x141fffff] mem +PCI: 00:1c.1 20 * [0x14200000 - 0x142fffff] mem +PCI: 00:02.0 10 * [0x14300000 - 0x1437ffff] mem +PCI: 00:02.1 10 * [0x14380000 - 0x143fffff] mem +PCI: 00:02.0 1c * [0x14400000 - 0x1443ffff] mem +PCI: 00:1b.0 10 * [0x14440000 - 0x14443fff] mem +PCI: 00:1d.7 10 * [0x14444000 - 0x144443ff] mem +PCI: 00:1f.2 24 * [0x14444400 - 0x144447ff] mem +DOMAIN: 0000 compute_resources_mem: base: 14444800 size: 14444800 align: 28 gran: 0 limit: ffffffff done +avoid_fixed_resources: DOMAIN: 0000 +avoid_fixed_resources:@DOMAIN: 0000 10000000 limit 0000ffff +avoid_fixed_resources:@DOMAIN: 0000 10000100 limit ffffffff +constrain_resources: DOMAIN: 0000 +constrain_resources: PCI: 00:00.0 +constrain_resources: PCI: 00:02.0 +constrain_resources: PCI: 00:02.1 +constrain_resources: PCI: 00:1b.0 +constrain_resources: PCI: 00:1c.0 +constrain_resources: PCI: 01:00.0 +constrain_resources: PCI: 00:1c.1 +constrain_resources: PCI: 02:00.0 +constrain_resources: PCI: 00:1c.2 +constrain_resources: PCI: 00:1c.3 +constrain_resources: PCI: 00:1d.0 +constrain_resources: PCI: 00:1d.1 +constrain_resources: PCI: 00:1d.2 +constrain_resources: PCI: 00:1d.3 +constrain_resources: PCI: 00:1d.7 +constrain_resources: PCI: 00:1e.0 +constrain_resources: PCI: 05:00.0 +constrain_resources: PCI: 05:00.1 +constrain_resources: PCI: 05:00.2 +constrain_resources: PCI: 05:00.3 +constrain_resources: PCI: 00:1f.0 +constrain_resources: PNP: 00ff.1 +constrain_resources: PNP: 00ff.2 +skipping PNP: 00ff.2@60 fixed resource, size=0! +skipping PNP: 00ff.2@62 fixed resource, size=0! +skipping PNP: 00ff.2@64 fixed resource, size=0! +skipping PNP: 00ff.2@66 fixed resource, size=0! +constrain_resources: PNP: 164e.2 +constrain_resources: PNP: 164e.7 +constrain_resources: PNP: 164e.19 +constrain_resources: PNP: 002e.1 +constrain_resources: PNP: 002e.3 +constrain_resources: PNP: 002e.7 +constrain_resources: PCI: 00:1f.1 +constrain_resources: PCI: 00:1f.2 +constrain_resources: PCI: 00:1f.3 +constrain_resources: I2C: 01:69 +constrain_resources: I2C: 01:54 +constrain_resources: I2C: 01:55 +constrain_resources: I2C: 01:56 +constrain_resources: I2C: 01:57 +constrain_resources: I2C: 01:5c +constrain_resources: I2C: 01:5d +constrain_resources: I2C: 01:5e +constrain_resources: I2C: 01:5f +avoid_fixed_resources2: DOMAIN: 0000@10000000 limit 0000ffff + lim->base 00001690 lim->limit 0000ffff +avoid_fixed_resources2: DOMAIN: 0000@10000100 limit ffffffff + lim->base 00000000 lim->limit efffffff +Setting resources... +DOMAIN: 0000 allocate_resources_io: base:1690 size:30d8 align:12 gran:0 limit:ffff +Assigned: PCI: 00:1e.0 1c * [0x2000 - 0x3fff] io +Assigned: PCI: 00:1c.0 1c * [0x4000 - 0x4fff] io +Assigned: PCI: 00:1d.0 20 * [0x5000 - 0x501f] io +Assigned: PCI: 00:1d.1 20 * [0x5020 - 0x503f] io +Assigned: PCI: 00:1d.2 20 * [0x5040 - 0x505f] io +Assigned: PCI: 00:1d.3 20 * [0x5060 - 0x507f] io +Assigned: PCI: 00:1f.1 20 * [0x5080 - 0x508f] io +Assigned: PCI: 00:1f.2 20 * [0x5090 - 0x509f] io +Assigned: PCI: 00:02.0 14 * [0x50a0 - 0x50a7] io +Assigned: PCI: 00:1f.1 10 * [0x50a8 - 0x50af] io +Assigned: PCI: 00:1f.1 18 * [0x50b0 - 0x50b7] io +Assigned: PCI: 00:1f.2 10 * [0x50b8 - 0x50bf] io +Assigned: PCI: 00:1f.2 18 * [0x50c0 - 0x50c7] io +Assigned: PCI: 00:1f.1 14 * [0x50c8 - 0x50cb] io +Assigned: PCI: 00:1f.1 1c * [0x50cc - 0x50cf] io +Assigned: PCI: 00:1f.2 14 * [0x50d0 - 0x50d3] io +Assigned: PCI: 00:1f.2 1c * [0x50d4 - 0x50d7] io +DOMAIN: 0000 allocate_resources_io: next_base: 50d8 size: 30d8 align: 12 gran: 0 done +PCI: 00:1c.0 allocate_resources_io: base:4000 size:1000 align:12 gran:12 limit:ffff +Assigned: PCI: 01:00.0 18 * [0x4000 - 0x401f] io +PCI: 00:1c.0 allocate_resources_io: next_base: 4020 size: 1000 align: 12 gran: 12 done +PCI: 00:1c.1 allocate_resources_io: base:ffff size:0 align:12 gran:12 limit:ffff +PCI: 00:1c.1 allocate_resources_io: next_base: ffff size: 0 align: 12 gran: 12 done +PCI: 00:1c.2 allocate_resources_io: base:ffff size:0 align:12 gran:12 limit:ffff +PCI: 00:1c.2 allocate_resources_io: next_base: ffff size: 0 align: 12 gran: 12 done +PCI: 00:1c.3 allocate_resources_io: base:ffff size:0 align:12 gran:12 limit:ffff +PCI: 00:1c.3 allocate_resources_io: next_base: ffff size: 0 align: 12 gran: 12 done +PCI: 00:1e.0 allocate_resources_io: base:2000 size:2000 align:12 gran:12 limit:ffff +Assigned: PCI: 05:00.0 2c * [0x2000 - 0x2fff] io +Assigned: PCI: 05:00.0 34 * [0x3000 - 0x3fff] io +PCI: 00:1e.0 allocate_resources_io: next_base: 4000 size: 2000 align: 12 gran: 12 done +DOMAIN: 0000 allocate_resources_mem: base:d0000000 size:14444800 align:28 gran:0 limit:efffffff +Assigned: PCI: 00:02.0 18 * [0xd0000000 - 0xdfffffff] prefmem +Assigned: PCI: 00:1e.0 20 * [0xe0000000 - 0xe20fffff] mem +Assigned: PCI: 00:1e.0 24 * [0xe2100000 - 0xe40fffff] prefmem +Assigned: PCI: 00:1c.0 20 * [0xe4100000 - 0xe41fffff] mem +Assigned: PCI: 00:1c.1 20 * [0xe4200000 - 0xe42fffff] mem +Assigned: PCI: 00:02.0 10 * [0xe4300000 - 0xe437ffff] mem +Assigned: PCI: 00:02.1 10 * [0xe4380000 - 0xe43fffff] mem +Assigned: PCI: 00:02.0 1c * [0xe4400000 - 0xe443ffff] mem +Assigned: PCI: 00:1b.0 10 * [0xe4440000 - 0xe4443fff] mem +Assigned: PCI: 00:1d.7 10 * [0xe4444000 - 0xe44443ff] mem +Assigned: PCI: 00:1f.2 24 * [0xe4444400 - 0xe44447ff] mem +DOMAIN: 0000 allocate_resources_mem: next_base: e4444800 size: 14444800 align: 28 gran: 0 done +PCI: 00:1c.0 allocate_resources_prefmem: base:efffffff size:0 align:20 gran:20 limit:efffffff +PCI: 00:1c.0 allocate_resources_prefmem: next_base: efffffff size: 0 align: 20 gran: 20 done +PCI: 00:1c.0 allocate_resources_mem: base:e4100000 size:100000 align:20 gran:20 limit:efffffff +Assigned: PCI: 01:00.0 10 * [0xe4100000 - 0xe411ffff] mem +PCI: 00:1c.0 allocate_resources_mem: next_base: e4120000 size: 100000 align: 20 gran: 20 done +PCI: 00:1c.1 allocate_resources_prefmem: base:efffffff size:0 align:20 gran:20 limit:efffffff +PCI: 00:1c.1 allocate_resources_prefmem: next_base: efffffff size: 0 align: 20 gran: 20 done +PCI: 00:1c.1 allocate_resources_mem: base:e4200000 size:100000 align:20 gran:20 limit:efffffff +Assigned: PCI: 02:00.0 10 * [0xe4200000 - 0xe420ffff] mem +PCI: 00:1c.1 allocate_resources_mem: next_base: e4210000 size: 100000 align: 20 gran: 20 done +PCI: 00:1c.2 allocate_resources_prefmem: base:efffffff size:0 align:20 gran:20 limit:efffffff +PCI: 00:1c.2 allocate_resources_prefmem: next_base: efffffff size: 0 align: 20 gran: 20 done +PCI: 00:1c.2 allocate_resources_mem: base:efffffff size:0 align:20 gran:20 limit:efffffff +PCI: 00:1c.2 allocate_resources_mem: next_base: efffffff size: 0 align: 20 gran: 20 done +PCI: 00:1c.3 allocate_resources_prefmem: base:efffffff size:0 align:20 gran:20 limit:efffffff +PCI: 00:1c.3 allocate_resources_prefmem: next_base: efffffff size: 0 align: 20 gran: 20 done +PCI: 00:1c.3 allocate_resources_mem: base:efffffff size:0 align:20 gran:20 limit:efffffff +PCI: 00:1c.3 allocate_resources_mem: next_base: efffffff size: 0 align: 20 gran: 20 done +PCI: 00:1e.0 allocate_resources_prefmem: base:e2100000 size:2000000 align:20 gran:20 limit:efffffff +Assigned: PCI: 05:00.0 1c * [0xe2100000 - 0xe40fffff] prefmem +PCI: 00:1e.0 allocate_resources_prefmem: next_base: e4100000 size: 2000000 align: 20 gran: 20 done +PCI: 00:1e.0 allocate_resources_mem: base:e0000000 size:2100000 align:20 gran:20 limit:efffffff +Assigned: PCI: 05:00.0 24 * [0xe0000000 - 0xe1ffffff] mem +Assigned: PCI: 05:00.0 10 * [0xe2000000 - 0xe2000fff] mem +Assigned: PCI: 05:00.1 10 * [0xe2001000 - 0xe20017ff] mem +Assigned: PCI: 05:00.2 10 * [0xe2001800 - 0xe20018ff] mem +Assigned: PCI: 05:00.3 10 * [0xe2001900 - 0xe20019ff] mem +PCI: 00:1e.0 allocate_resources_mem: next_base: e2001a00 size: 2100000 align: 20 gran: 20 done +Root Device assign_resources, bus 0 link: 0 +pci_tolm: 0xd0000000 +Base of stolen memory: 0xbf800000 +Top of Low Used DRAM: 0xc0000000 +IGD decoded, subtracting 8M UMA +Available memory: 3137536K (3064M) +Adding PCIe config bar +DOMAIN: 0000 assign_resources, bus 0 link: 0 +PCI: 00:00.0 cf <- [0x00f0000000 - 0x00f3ffffff] size 0x04000000 gran 0x00 mem<mmconfig> +PCI: 00:02.0 10 <- [0x00e4300000 - 0x00e437ffff] size 0x00080000 gran 0x13 mem +PCI: 00:02.0 14 <- [0x00000050a0 - 0x00000050a7] size 0x00000008 gran 0x03 io +PCI: 00:02.0 18 <- [0x00d0000000 - 0x00dfffffff] size 0x10000000 gran 0x1c prefmem +PCI: 00:02.0 1c <- [0x00e4400000 - 0x00e443ffff] size 0x00040000 gran 0x12 mem +PCI: 00:02.1 10 <- [0x00e4380000 - 0x00e43fffff] size 0x00080000 gran 0x13 mem +PCI: 00:1b.0 10 <- [0x00e4440000 - 0x00e4443fff] size 0x00004000 gran 0x0e mem64 +PCI: 00:1c.0 1c <- [0x0000004000 - 0x0000004fff] size 0x00001000 gran 0x0c bus 01 io +PCI: 00:1c.0 24 <- [0x00efffffff - 0x00effffffe] size 0x00000000 gran 0x14 bus 01 prefmem +PCI: 00:1c.0 20 <- [0x00e4100000 - 0x00e41fffff] size 0x00100000 gran 0x14 bus 01 mem +PCI: 00:1c.0 assign_resources, bus 1 link: 0 +PCI: 01:00.0 10 <- [0x00e4100000 - 0x00e411ffff] size 0x00020000 gran 0x11 mem +PCI: 01:00.0 18 <- [0x0000004000 - 0x000000401f] size 0x00000020 gran 0x05 io +PCI: 00:1c.0 assign_resources, bus 1 link: 0 +PCI: 00:1c.1 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 02 io +PCI: 00:1c.1 24 <- [0x00efffffff - 0x00effffffe] size 0x00000000 gran 0x14 bus 02 prefmem +PCI: 00:1c.1 20 <- [0x00e4200000 - 0x00e42fffff] size 0x00100000 gran 0x14 bus 02 mem +PCI: 00:1c.1 assign_resources, bus 2 link: 0 +PCI: 02:00.0 10 <- [0x00e4200000 - 0x00e420ffff] size 0x00010000 gran 0x10 mem64 +PCI: 00:1c.1 assign_resources, bus 2 link: 0 +PCI: 00:1c.2 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 03 io +PCI: 00:1c.2 24 <- [0x00efffffff - 0x00effffffe] size 0x00000000 gran 0x14 bus 03 prefmem +PCI: 00:1c.2 20 <- [0x00efffffff - 0x00effffffe] size 0x00000000 gran 0x14 bus 03 mem +PCI: 00:1c.3 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 04 io +PCI: 00:1c.3 24 <- [0x00efffffff - 0x00effffffe] size 0x00000000 gran 0x14 bus 04 prefmem +PCI: 00:1c.3 20 <- [0x00efffffff - 0x00effffffe] size 0x00000000 gran 0x14 bus 04 mem +PCI: 00:1d.0 20 <- [0x0000005000 - 0x000000501f] size 0x00000020 gran 0x05 io +PCI: 00:1d.1 20 <- [0x0000005020 - 0x000000503f] size 0x00000020 gran 0x05 io +PCI: 00:1d.2 20 <- [0x0000005040 - 0x000000505f] size 0x00000020 gran 0x05 io +PCI: 00:1d.3 20 <- [0x0000005060 - 0x000000507f] size 0x00000020 gran 0x05 io +PCI: 00:1d.7 10 <- [0x00e4444000 - 0x00e44443ff] size 0x00000400 gran 0x0a mem +PCI: 00:1e.0 1c <- [0x0000002000 - 0x0000003fff] size 0x00002000 gran 0x0c bus 05 io +PCI: 00:1e.0 24 <- [0x00e2100000 - 0x00e40fffff] size 0x02000000 gran 0x14 bus 05 prefmem +PCI: 00:1e.0 20 <- [0x00e0000000 - 0x00e20fffff] size 0x02100000 gran 0x14 bus 05 mem +PCI: 00:1e.0 assign_resources, bus 5 link: 0 +PCI: 05:00.0 In set resources +PCI: 05:00.0 10 <- [0x00e2000000 - 0x00e2000fff] size 0x00001000 gran 0x0c mem +PCI: 05:00.0 2c <- [0x0000002000 - 0x0000002fff] size 0x00001000 gran 0x02 io +PCI: 05:00.0 34 <- [0x0000003000 - 0x0000003fff] size 0x00001000 gran 0x02 io +PCI: 05:00.0 1c <- [0x00e2100000 - 0x00e40fffff] size 0x02000000 gran 0x0c prefmem +PCI: 05:00.0 24 <- [0x00e0000000 - 0x00e1ffffff] size 0x02000000 gran 0x0c mem +PCI: 05:00.1 10 <- [0x00e2001000 - 0x00e20017ff] size 0x00000800 gran 0x0b mem +PCI: 05:00.2 10 <- [0x00e2001800 - 0x00e20018ff] size 0x00000100 gran 0x08 mem +PCI: 05:00.3 10 <- [0x00e2001900 - 0x00e20019ff] size 0x00000100 gran 0x08 mem +PCI: 00:1e.0 assign_resources, bus 5 link: 0 +PCI: 00:1f.0 assign_resources, bus 0 link: 0 +PNP: 00ff.1 missing set_resources +PNP: 00ff.2 missing set_resources +PNP: 164e.2 60 <- [0x00000002f8 - 0x00000002ff] size 0x00000008 gran 0x03 io +ERROR: PNP: 164e.2 70 irq size: 0x0000000001 not assigned +ERROR: PNP: 164e.2 74 drq size: 0x0000000001 not assigned +ERROR: PNP: 164e.2 75 drq size: 0x0000000001 not assigned +PNP: 164e.7 60 <- [0x0000001680 - 0x000000168f] size 0x00000010 gran 0x04 io +ERROR: PNP: 164e.7 70 irq size: 0x0000000001 not assigned +PNP: 164e.19 60 <- [0x000000164c - 0x000000164d] size 0x00000002 gran 0x01 io +ERROR: PNP: 164e.19 70 irq size: 0x0000000001 not assigned +PNP: 002e.1 60 <- [0x00000003bc - 0x00000007bb] size 0x00000400 gran 0x0a io +PNP: 002e.1 70 <- [0x0000000007 - 0x0000000007] size 0x00000001 gran 0x00 irq +ERROR: PNP: 002e.1 74 drq size: 0x0000000001 not assigned +PNP: 002e.3 60 <- [0x00000003f8 - 0x00000003ff] size 0x00000008 gran 0x03 io +PNP: 002e.3 70 <- [0x0000000004 - 0x0000000004] size 0x00000001 gran 0x00 irq +PNP: 002e.7 60 <- [0x0000001620 - 0x0000001627] size 0x00000008 gran 0x03 io +ERROR: PNP: 002e.7 70 irq size: 0x0000000001 not assigned +PCI: 00:1f.0 assign_resources, bus 0 link: 0 +PCI: 00:1f.1 10 <- [0x00000050a8 - 0x00000050af] size 0x00000008 gran 0x03 io +PCI: 00:1f.1 14 <- [0x00000050c8 - 0x00000050cb] size 0x00000004 gran 0x02 io +PCI: 00:1f.1 18 <- [0x00000050b0 - 0x00000050b7] size 0x00000008 gran 0x03 io +PCI: 00:1f.1 1c <- [0x00000050cc - 0x00000050cf] size 0x00000004 gran 0x02 io +PCI: 00:1f.1 20 <- [0x0000005080 - 0x000000508f] size 0x00000010 gran 0x04 io +PCI: 00:1f.2 10 <- [0x00000050b8 - 0x00000050bf] size 0x00000008 gran 0x03 io +PCI: 00:1f.2 14 <- [0x00000050d0 - 0x00000050d3] size 0x00000004 gran 0x02 io +PCI: 00:1f.2 18 <- [0x00000050c0 - 0x00000050c7] size 0x00000008 gran 0x03 io +PCI: 00:1f.2 1c <- [0x00000050d4 - 0x00000050d7] size 0x00000004 gran 0x02 io +PCI: 00:1f.2 20 <- [0x0000005090 - 0x000000509f] size 0x00000010 gran 0x04 io +PCI: 00:1f.2 24 <- [0x00e4444400 - 0x00e44447ff] size 0x00000400 gran 0x0a mem +PCI: 00:1f.3 assign_resources, bus 1 link: 0 +PCI: 00:1f.3 assign_resources, bus 1 link: 0 +DOMAIN: 0000 assign_resources, bus 0 link: 0 +CBMEM region bf6d0000-bf7fffff (cbmem_late_set_table) +Root Device assign_resources, bus 0 link: 0 +Done setting resources. +Show resources in subtree (Root Device)...After assigning values. + Root Device child on link 0 CPU_CLUSTER: 0 + CPU_CLUSTER: 0 child on link 0 APIC: 00 + APIC: 00 + DOMAIN: 0000 child on link 0 PCI: 00:00.0 + DOMAIN: 0000 resource base 1690 size 30d8 align 12 gran 0 limit ffff flags 40040100 index 10000000 + DOMAIN: 0000 resource base d0000000 size 14444800 align 28 gran 0 limit efffffff flags 40040200 index 10000100 + DOMAIN: 0000 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 3 + DOMAIN: 0000 resource base c0000 size bff40000 align 0 gran 0 limit 0 flags e0004200 index 4 + DOMAIN: 0000 resource base bf800000 size 800000 align 0 gran 0 limit 0 flags f0000200 index 5 + DOMAIN: 0000 resource base f0000000 size 4000000 align 0 gran 0 limit 0 flags f0000200 index 7 + PCI: 00:00.0 + PCI: 00:00.0 resource base f0000000 size 4000000 align 0 gran 0 limit 0 flags e0000200 index cf + PCI: 00:02.0 + PCI: 00:02.0 resource base e4300000 size 80000 align 19 gran 19 limit efffffff flags 60000200 index 10 + PCI: 00:02.0 resource base 50a0 size 8 align 3 gran 3 limit ffff flags 60000100 index 14 + PCI: 00:02.0 resource base d0000000 size 10000000 align 28 gran 28 limit efffffff flags 60001200 index 18 + PCI: 00:02.0 resource base e4400000 size 40000 align 18 gran 18 limit efffffff flags 60000200 index 1c + PCI: 00:02.1 + PCI: 00:02.1 resource base e4380000 size 80000 align 19 gran 19 limit efffffff flags 60000200 index 10 + PCI: 00:1b.0 + PCI: 00:1b.0 resource base e4440000 size 4000 align 14 gran 14 limit efffffff flags 60000201 index 10 + PCI: 00:1c.0 child on link 0 PCI: 01:00.0 + PCI: 00:1c.0 resource base 4000 size 1000 align 12 gran 12 limit ffff flags 60080102 index 1c + PCI: 00:1c.0 resource base efffffff size 0 align 20 gran 20 limit efffffff flags 60081202 index 24 + PCI: 00:1c.0 resource base e4100000 size 100000 align 20 gran 20 limit efffffff flags 60080202 index 20 + PCI: 01:00.0 + PCI: 01:00.0 resource base e4100000 size 20000 align 17 gran 17 limit efffffff flags 60000200 index 10 + PCI: 01:00.0 resource base 4000 size 20 align 5 gran 5 limit ffff flags 60000100 index 18 + PCI: 00:1c.1 child on link 0 PCI: 02:00.0 + PCI: 00:1c.1 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c + PCI: 00:1c.1 resource base efffffff size 0 align 20 gran 20 limit efffffff flags 60081202 index 24 + PCI: 00:1c.1 resource base e4200000 size 100000 align 20 gran 20 limit efffffff flags 60080202 index 20 + PCI: 02:00.0 + PCI: 02:00.0 resource base e4200000 size 10000 align 16 gran 16 limit efffffff flags 60000201 index 10 + PCI: 00:1c.2 + PCI: 00:1c.2 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c + PCI: 00:1c.2 resource base efffffff size 0 align 20 gran 20 limit efffffff flags 60081202 index 24 + PCI: 00:1c.2 resource base efffffff size 0 align 20 gran 20 limit efffffff flags 60080202 index 20 + PCI: 00:1c.3 + PCI: 00:1c.3 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c + PCI: 00:1c.3 resource base efffffff size 0 align 20 gran 20 limit efffffff flags 60081202 index 24 + PCI: 00:1c.3 resource base efffffff size 0 align 20 gran 20 limit efffffff flags 60080202 index 20 + PCI: 00:1d.0 + PCI: 00:1d.0 resource base 5000 size 20 align 5 gran 5 limit ffff flags 60000100 index 20 + PCI: 00:1d.1 + PCI: 00:1d.1 resource base 5020 size 20 align 5 gran 5 limit ffff flags 60000100 index 20 + PCI: 00:1d.2 + PCI: 00:1d.2 resource base 5040 size 20 align 5 gran 5 limit ffff flags 60000100 index 20 + PCI: 00:1d.3 + PCI: 00:1d.3 resource base 5060 size 20 align 5 gran 5 limit ffff flags 60000100 index 20 + PCI: 00:1d.7 + PCI: 00:1d.7 resource base e4444000 size 400 align 10 gran 10 limit efffffff flags 60000200 index 10 + PCI: 00:1e.0 child on link 0 PCI: 05:00.0 + PCI: 00:1e.0 resource base 2000 size 2000 align 12 gran 12 limit ffff flags 60080102 index 1c + PCI: 00:1e.0 resource base e2100000 size 2000000 align 20 gran 20 limit efffffff flags 60081202 index 24 + PCI: 00:1e.0 resource base e0000000 size 2100000 align 20 gran 20 limit efffffff flags 60080202 index 20 + PCI: 05:00.0 + PCI: 05:00.0 resource base e2000000 size 1000 align 12 gran 12 limit efffffff flags 60000200 index 10 + PCI: 05:00.0 resource base 2000 size 1000 align 2 gran 2 limit ffff flags 60000100 index 2c + PCI: 05:00.0 resource base 3000 size 1000 align 2 gran 2 limit ffff flags 60000100 index 34 + PCI: 05:00.0 resource base e2100000 size 2000000 align 12 gran 12 limit efffffff flags 60001200 index 1c + PCI: 05:00.0 resource base e0000000 size 2000000 align 12 gran 12 limit efffffff flags 60000200 index 24 + PCI: 05:00.1 + PCI: 05:00.1 resource base e2001000 size 800 align 11 gran 11 limit efffffff flags 60000200 index 10 + PCI: 05:00.2 + PCI: 05:00.2 resource base e2001800 size 100 align 8 gran 8 limit efffffff flags 60000200 index 10 + PCI: 05:00.3 + PCI: 05:00.3 resource base e2001900 size 100 align 8 gran 8 limit efffffff flags 60000200 index 10 + PCI: 00:1f.0 child on link 0 PNP: 00ff.1 + PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000 + PCI: 00:1f.0 resource base ff800000 size 800000 align 0 gran 0 limit 0 flags c0040200 index 10000100 + PCI: 00:1f.0 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3 + PNP: 00ff.1 + PNP: 00ff.1 resource base 15e0 size 10 align 5 gran 5 limit 0 flags 80000100 index 77 + PNP: 00ff.2 + PNP: 00ff.2 resource base 62 size 0 align 0 gran 0 limit 0 flags c0000100 index 60 + PNP: 00ff.2 resource base 66 size 0 align 0 gran 0 limit 0 flags c0000100 index 62 + PNP: 00ff.2 resource base 1600 size 0 align 0 gran 0 limit 0 flags c0000100 index 64 + PNP: 00ff.2 resource base 1604 size 0 align 0 gran 0 limit 0 flags c0000100 index 66 + PNP: 164e.2 + PNP: 164e.2 resource base 2f8 size 8 align 3 gran 3 limit 7ff flags e0000100 index 60 + PNP: 164e.2 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 + PNP: 164e.2 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74 + PNP: 164e.2 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 75 + PNP: 164e.3 + PNP: 164e.3 resource base 3f8 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60 + PNP: 164e.3 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 + PNP: 164e.7 + PNP: 164e.7 resource base 1680 size 10 align 4 gran 4 limit ffff flags e0000100 index 60 + PNP: 164e.7 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 + PNP: 164e.19 + PNP: 164e.19 resource base 164c size 2 align 1 gran 1 limit ffff flags e0000100 index 60 + PNP: 164e.19 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 + PNP: 002e.0 + PNP: 002e.0 resource base 0 size 8 align 3 gran 3 limit 7ff flags 100 index 60 + PNP: 002e.0 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 + PNP: 002e.0 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74 + PNP: 002e.1 + PNP: 002e.1 resource base 3bc size 400 align 10 gran 10 limit 7ff flags e0000100 index 60 + PNP: 002e.1 resource base 7 size 1 align 0 gran 0 limit 0 flags e0000400 index 70 + PNP: 002e.1 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74 + PNP: 002e.2 + PNP: 002e.2 resource base 2f8 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60 + PNP: 002e.2 resource base 4 size 1 align 0 gran 0 limit 0 flags c0000400 index 70 + PNP: 002e.2 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74 + PNP: 002e.2 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 75 + PNP: 002e.3 + PNP: 002e.3 resource base 3f8 size 8 align 3 gran 3 limit 7ff flags e0000100 index 60 + PNP: 002e.3 resource base 4 size 1 align 0 gran 0 limit 0 flags e0000400 index 70 + PNP: 002e.7 + PNP: 002e.7 resource base 1620 size 8 align 3 gran 3 limit ffff flags e0000100 index 60 + PNP: 002e.7 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 + PNP: 002e.a + PNP: 002e.a resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 60 + PNP: 002e.a resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 + PCI: 00:1f.1 + PCI: 00:1f.1 resource base 50a8 size 8 align 3 gran 3 limit ffff flags 60000100 index 10 + PCI: 00:1f.1 resource base 50c8 size 4 align 2 gran 2 limit ffff flags 60000100 index 14 + PCI: 00:1f.1 resource base 50b0 size 8 align 3 gran 3 limit ffff flags 60000100 index 18 + PCI: 00:1f.1 resource base 50cc size 4 align 2 gran 2 limit ffff flags 60000100 index 1c + PCI: 00:1f.1 resource base 5080 size 10 align 4 gran 4 limit ffff flags 60000100 index 20 + PCI: 00:1f.2 + PCI: 00:1f.2 resource base 50b8 size 8 align 3 gran 3 limit ffff flags 60000100 index 10 + PCI: 00:1f.2 resource base 50d0 size 4 align 2 gran 2 limit ffff flags 60000100 index 14 + PCI: 00:1f.2 resource base 50c0 size 8 align 3 gran 3 limit ffff flags 60000100 index 18 + PCI: 00:1f.2 resource base 50d4 size 4 align 2 gran 2 limit ffff flags 60000100 index 1c + PCI: 00:1f.2 resource base 5090 size 10 align 4 gran 4 limit ffff flags 60000100 index 20 + PCI: 00:1f.2 resource base e4444400 size 400 align 10 gran 10 limit efffffff flags 60000200 index 24 + PCI: 00:1f.3 child on link 0 I2C: 01:69 + PCI: 00:1f.3 resource base 400 size 20 align 0 gran 0 limit 41f flags f0000100 index 20 + I2C: 01:69 + I2C: 01:54 + I2C: 01:55 + I2C: 01:56 + I2C: 01:57 + I2C: 01:5c + I2C: 01:5d + I2C: 01:5e + I2C: 01:5f +Done allocating resources. +BS: Exiting BS_DEV_RESOURCES state. +BS: BS_DEV_RESOURCES times (us): entry 0 run 3353806 exit 0 +BS: Entering BS_DEV_ENABLE state. +Enabling resources... +PCI: 00:00.0 subsystem <- 17aa/2017 +PCI: 00:00.0 cmd <- 06 +PCI: 00:02.0 subsystem <- 17aa/201a +PCI: 00:02.0 cmd <- 03 +PCI: 00:02.1 subsystem <- 17aa/201a +PCI: 00:02.1 cmd <- 02 +PCI: 00:1b.0 subsystem <- 17aa/2010 +PCI: 00:1b.0 cmd <- 102 +PCI: 00:1c.0 bridge ctrl <- 0003 +PCI: 00:1c.0 subsystem <- 0000/0000 +PCI: 00:1c.0 cmd <- 107 +PCI: 00:1c.1 bridge ctrl <- 0003 +PCI: 00:1c.1 subsystem <- 0000/0000 +PCI: 00:1c.1 cmd <- 106 +PCI: 00:1c.2 bridge ctrl <- 0003 +PCI: 00:1c.2 cmd <- 00 +PCI: 00:1c.3 bridge ctrl <- 0003 +PCI: 00:1c.3 cmd <- 00 +PCI: 00:1d.0 subsystem <- 17aa/200a +PCI: 00:1d.0 cmd <- 01 +PCI: 00:1d.1 subsystem <- 17aa/200a +PCI: 00:1d.1 cmd <- 01 +PCI: 00:1d.2 subsystem <- 17aa/200a +PCI: 00:1d.2 cmd <- 01 +PCI: 00:1d.3 subsystem <- 17aa/200a +PCI: 00:1d.3 cmd <- 01 +PCI: 00:1d.7 subsystem <- 17aa/200b +PCI: 00:1d.7 cmd <- 102 +PCI: 00:1e.0 bridge ctrl <- 0003 +PCI: 00:1e.0 cmd <- 07 (NOT WRITTEN!) +PCI: 00:1f.0 subsystem <- 17aa/2009 +PCI: 00:1f.0 cmd <- 107 +PCI: 00:1f.1 subsystem <- 17aa/200c +PCI: 00:1f.1 cmd <- 01 +PCI: 00:1f.2 subsystem <- 17aa/200d +PCI: 00:1f.2 cmd <- 03 +PCI: 00:1f.3 subsystem <- 17aa/200f +PCI: 00:1f.3 cmd <- 101 +PCI: 01:00.0 cmd <- 03 +PCI: 02:00.0 cmd <- 02 +PCI: 05:00.0 bridge ctrl <- 0503 +PCI: 05:00.0 cmd <- 03 +PCI: 05:00.1 cmd <- 02 +PCI: 05:00.2 cmd <- 06 +PCI: 05:00.3 cmd <- 06 +done. +BS: Exiting BS_DEV_ENABLE state. +BS: BS_DEV_ENABLE times (us): entry 0 run 124473 exit 0 +BS: Entering BS_DEV_INIT state. +Initializing devices... +Root Device init +recv_ec_data: 0x11 +recv_ec_data: 0x11 +Root Device init 5804 usecs +CPU_CLUSTER: 0 init +start_eip=0x00001000, code_size=0x00000031 +Initializing SMM handler... ... pmbase = 0x0500 + +SMI_STS: MCSMI PM1 +PM1_STS: WAK PWRBTN TMROF +GPE0_STS: GPIO15 GPIO14 GPIO13 GPIO12 GPIO11 GPIO10 GPIO8 GPIO7 GPIO6 GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0 +ALT_GP_SMI_STS: GPI15 GPI14 GPI13 GPI12 GPI11 GPI10 GPI8 GPI7 GPI6 GPI5 GPI4 GPI3 GPI2 GPI1 GPI0 +TCO_STS: INTRD_DET + ... raise SMI# +Initializing CPU #0 +CPU: vendor Intel device 6ec +CPU: family 06, model 0e, stepping 0c +Enabling cache +microcode: sig=0x6ec pf=0x20 revision=0x0 +Microcode size field is 0 +Microcode size field is 0 +Microcode size field is 0 +Microcode size field is 0 +microcode: updated to revision 0x54 date=2006-05-01 +CPU: Intel(R) Core(TM) Duo CPU L2400 @ 1.66GHz. +MTRR: Physical address space: +0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6 +0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0 +0x00000000000c0000 - 0x00000000bf800000 size 0xbf740000 type 6 +0x00000000bf800000 - 0x00000000d0000000 size 0x10800000 type 0 +0x00000000d0000000 - 0x00000000e0000000 size 0x10000000 type 1 +0x00000000e0000000 - 0x0000000100000000 size 0x20000000 type 0 +MTRR addr 0x0-0x10 set to 6 type @ 0 +MTRR addr 0x10-0x20 set to 6 type @ 1 +MTRR addr 0x20-0x30 set to 6 type @ 2 +MTRR addr 0x30-0x40 set to 6 type @ 3 +MTRR addr 0x40-0x50 set to 6 type @ 4 +MTRR addr 0x50-0x60 set to 6 type @ 5 +MTRR addr 0x60-0x70 set to 6 type @ 6 +MTRR addr 0x70-0x80 set to 6 type @ 7 +MTRR addr 0x80-0x84 set to 6 type @ 8 +MTRR addr 0x84-0x88 set to 6 type @ 9 +MTRR addr 0x88-0x8c set to 6 type @ 10 +MTRR addr 0x8c-0x90 set to 6 type @ 11 +MTRR addr 0x90-0x94 set to 6 type @ 12 +MTRR addr 0x94-0x98 set to 6 type @ 13 +MTRR addr 0x98-0x9c set to 6 type @ 14 +MTRR addr 0x9c-0xa0 set to 6 type @ 15 +MTRR addr 0xa0-0xa4 set to 0 type @ 16 +MTRR addr 0xa4-0xa8 set to 0 type @ 17 +MTRR addr 0xa8-0xac set to 0 type @ 18 +MTRR addr 0xac-0xb0 set to 0 type @ 19 +MTRR addr 0xb0-0xb4 set to 0 type @ 20 +MTRR addr 0xb4-0xb8 set to 0 type @ 21 +MTRR addr 0xb8-0xbc set to 0 type @ 22 +MTRR addr 0xbc-0xc0 set to 0 type @ 23 +MTRR addr 0xc0-0xc1 set to 6 type @ 24 +MTRR addr 0xc1-0xc2 set to 6 type @ 25 +MTRR addr 0xc2-0xc3 set to 6 type @ 26 +MTRR addr 0xc3-0xc4 set to 6 type @ 27 +MTRR addr 0xc4-0xc5 set to 6 type @ 28 +MTRR addr 0xc5-0xc6 set to 6 type @ 29 +MTRR addr 0xc6-0xc7 set to 6 type @ 30 +MTRR addr 0xc7-0xc8 set to 6 type @ 31 +MTRR addr 0xc8-0xc9 set to 6 type @ 32 +MTRR addr 0xc9-0xca set to 6 type @ 33 +MTRR addr 0xca-0xcb set to 6 type @ 34 +MTRR addr 0xcb-0xcc set to 6 type @ 35 +MTRR addr 0xcc-0xcd set to 6 type @ 36 +MTRR addr 0xcd-0xce set to 6 type @ 37 +MTRR addr 0xce-0xcf set to 6 type @ 38 +MTRR addr 0xcf-0xd0 set to 6 type @ 39 +MTRR addr 0xd0-0xd1 set to 6 type @ 40 +MTRR addr 0xd1-0xd2 set to 6 type @ 41 +MTRR addr 0xd2-0xd3 set to 6 type @ 42 +MTRR addr 0xd3-0xd4 set to 6 type @ 43 +MTRR addr 0xd4-0xd5 set to 6 type @ 44 +MTRR addr 0xd5-0xd6 set to 6 type @ 45 +MTRR addr 0xd6-0xd7 set to 6 type @ 46 +MTRR addr 0xd7-0xd8 set to 6 type @ 47 +MTRR addr 0xd8-0xd9 set to 6 type @ 48 +MTRR addr 0xd9-0xda set to 6 type @ 49 +MTRR addr 0xda-0xdb set to 6 type @ 50 +MTRR addr 0xdb-0xdc set to 6 type @ 51 +MTRR addr 0xdc-0xdd set to 6 type @ 52 +MTRR addr 0xdd-0xde set to 6 type @ 53 +MTRR addr 0xde-0xdf set to 6 type @ 54 +MTRR addr 0xdf-0xe0 set to 6 type @ 55 +MTRR addr 0xe0-0xe1 set to 6 type @ 56 +MTRR addr 0xe1-0xe2 set to 6 type @ 57 +MTRR addr 0xe2-0xe3 set to 6 type @ 58 +MTRR addr 0xe3-0xe4 set to 6 type @ 59 +MTRR addr 0xe4-0xe5 set to 6 type @ 60 +MTRR addr 0xe5-0xe6 set to 6 type @ 61 +MTRR addr 0xe6-0xe7 set to 6 type @ 62 +MTRR addr 0xe7-0xe8 set to 6 type @ 63 +MTRR addr 0xe8-0xe9 set to 6 type @ 64 +MTRR addr 0xe9-0xea set to 6 type @ 65 +MTRR addr 0xea-0xeb set to 6 type @ 66 +MTRR addr 0xeb-0xec set to 6 type @ 67 +MTRR addr 0xec-0xed set to 6 type @ 68 +MTRR addr 0xed-0xee set to 6 type @ 69 +MTRR addr 0xee-0xef set to 6 type @ 70 +MTRR addr 0xef-0xf0 set to 6 type @ 71 +MTRR addr 0xf0-0xf1 set to 6 type @ 72 +MTRR addr 0xf1-0xf2 set to 6 type @ 73 +MTRR addr 0xf2-0xf3 set to 6 type @ 74 +MTRR addr 0xf3-0xf4 set to 6 type @ 75 +MTRR addr 0xf4-0xf5 set to 6 type @ 76 +MTRR addr 0xf5-0xf6 set to 6 type @ 77 +MTRR addr 0xf6-0xf7 set to 6 type @ 78 +MTRR addr 0xf7-0xf8 set to 6 type @ 79 +MTRR addr 0xf8-0xf9 set to 6 type @ 80 +MTRR addr 0xf9-0xfa set to 6 type @ 81 +MTRR addr 0xfa-0xfb set to 6 type @ 82 +MTRR addr 0xfb-0xfc set to 6 type @ 83 +MTRR addr 0xfc-0xfd set to 6 type @ 84 +MTRR addr 0xfd-0xfe set to 6 type @ 85 +MTRR addr 0xfe-0xff set to 6 type @ 86 +MTRR addr 0xff-0x100 set to 6 type @ 87 +MTRR: Fixed MSR 0x250 0x0606060606060606 +MTRR: Fixed MSR 0x258 0x0606060606060606 +MTRR: Fixed MSR 0x259 0x0000000000000000 +MTRR: Fixed MSR 0x268 0x0606060606060606 +MTRR: Fixed MSR 0x269 0x0606060606060606 +MTRR: Fixed MSR 0x26a 0x0606060606060606 +MTRR: Fixed MSR 0x26b 0x0606060606060606 +MTRR: Fixed MSR 0x26c 0x0606060606060606 +MTRR: Fixed MSR 0x26d 0x0606060606060606 +MTRR: Fixed MSR 0x26e 0x0606060606060606 +MTRR: Fixed MSR 0x26f 0x0606060606060606 +call enable_fixed_mtrr() +CPU physical address size: 32 bits +MTRR: default type WB/UC MTRR counts: 4/4. +MTRR: UC selected as default type. +MTRR: 0 base 0x0000000000000000 mask 0x0000000080000000 type 6 +MTRR: 1 base 0x0000000080000000 mask 0x00000000c0000000 type 6 +MTRR: 2 base 0x00000000bf800000 mask 0x00000000ff800000 type 0 +MTRR: 3 base 0x00000000d0000000 mask 0x00000000f0000000 type 1 + +MTRR check +Fixed MTRRs : Enabled +Variable MTRRs: Enabled + +Setting up local apic... apic_id: 0x00 done. +CPU: 0 2 siblings +CPU: 0 has sibling 1 +CPU #0 initialized +CPU1: stack_base 00160000, stack_end 00160ff8 +Asserting INIT. +Waiting for send to finish... ++Deasserting INIT. +Waiting for send to finish... ++#startup loops: 2. +Sending STARTUP #1 to 1. +After apic_write. +Startup point 1. +Waiting for send to finish... ++Sending STARTUP #2 to 1. +After apic_write. +Startup point 1. +Waiting for send to finish... ++After Startup. +Initializing CPU #1 +Waiting for 1 CPUS to stop +CPU: vendor Intel device 6ec +CPU: family 06, model 0e, stepping 0c +Enabling cache +microcode: sig=0x6ec pf=0x20 revision=0x0 +Microcode size field is 0 +Microcode size field is 0 +Microcode size field is 0 +Microcode size field is 0 +microcode: updated to revision 0x54 date=2006-05-01 +CPU: Intel(R) Core(TM) Duo CPU L2400 @ 1.66GHz. +MTRR: Fixed MSR 0x250 0x0606060606060606 +MTRR: Fixed MSR 0x258 0x0606060606060606 +MTRR: Fixed MSR 0x259 0x0000000000000000 +MTRR: Fixed MSR 0x268 0x0606060606060606 +MTRR: Fixed MSR 0x269 0x0606060606060606 +MTRR: Fixed MSR 0x26a 0x0606060606060606 +MTRR: Fixed MSR 0x26b 0x0606060606060606 +MTRR: Fixed MSR 0x26c 0x0606060606060606 +MTRR: Fixed MSR 0x26d 0x0606060606060606 +MTRR: Fixed MSR 0x26e 0x0606060606060606 +MTRR: Fixed MSR 0x26f 0x0606060606060606 +call enable_fixed_mtrr() +CPU physical address size: 32 bits +MTRR: 0 base 0x0000000000000000 mask 0x0000000080000000 type 6 +MTRR: 1 base 0x0000000080000000 mask 0x00000000c0000000 type 6 +MTRR: 2 base 0x00000000bf800000 mask 0x00000000ff800000 type 0 +MTRR: 3 base 0x00000000d0000000 mask 0x00000000f0000000 type 1 + +MTRR check +Fixed MTRRs : Enabled +Variable MTRRs: Enabled + +Setting up local apic... apic_id: 0x01 done. +CPU: 1 2 siblings +CPU #1 initialized +CPU 1 going down... +All AP CPUs stopped (11641 loops) +CPU1: stack: 00160000 - 00161000, lowest used address 00160c68, stack used: 920 bytes +CPU_CLUSTER: 0 init 687708 usecs +PCI: 00:00.0 init +Normal boot. +PCI: 00:00.0 init 2905 usecs +PCI: 00:02.0 init +Initializing VGA without OPROM. +GMADR=0xd0000008 GTTADR=0xe4400000 +i915lightup: graphics d0020000 mmio e4300000 addrport 50a0 physbase bf800000 +Extracted contents: +header: 00 ff ff ff ff ff ff 00 +serial number: 30 ae 00 40 00 00 00 00 00 0f +version: 01 03 +basic params: 80 19 12 78 ea +chroma info: ed 75 91 57 4f 8b 26 21 50 54 +established: 21 08 00 +standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 +descriptor 1: 28 15 00 40 41 00 26 30 18 88 36 00 f6 b9 00 00 00 18 +descriptor 2: ed 10 00 40 41 00 26 30 18 88 36 00 f6 b9 00 00 00 18 +descriptor 3: 00 00 00 0f 00 61 43 32 61 43 28 0f 01 00 4c a3 58 4a +descriptor 4: 00 00 00 fe 00 4c 54 4e 31 32 31 58 4a 2d 4c 30 37 0a +extensions: 00 +checksum: 00 + +Manufacturer: LEN Model 4000 Serial Number 0 +EDID version: 1.3 +Digital display +Maximum image size: 25 cm x 18 cm +Gamma: 220% +Check DPMS levels +DPMS levels: Standby Suspend Off +Supported color formats: RGB 4:4:4, YCrCb 4:2:2 +First detailed timing is preferred timing +Established timings supported: + 640x480@60Hz + 800x600@60Hz + 1024x768@60Hz +Standard timings supported: +Detailed timings +Hex of detail: 281500404100263018883600f6b900000018 +Did detailed timing +Detailed mode (IN HEX): Clock 54160 KHz, f6 mm x b9 mm + 0400 0418 04a0 0540 hborder 0 + 0300 0303 0309 0326 vborder 0 + -hsync -vsync +Hex of detail: ed1000404100263018883600f6b900000018 +Detailed mode (IN HEX): Clock 54160 KHz, f6 mm x b9 mm + 0400 0418 04a0 0540 hborder 0 + 0300 0303 0309 0326 vborder 0 + -hsync -vsync +Hex of detail: 0000000f006143326143280f01004ca3584a +Manufacturer-specified data, tag 15 +Hex of detail: 000000fe004c544e313231584a2d4c30370a +ASCII string: LTN121XJ +Checksum +Checksum: 0x0 (valid) + +Unknown extension block + +EDID block does NOT conform to EDID 1.3! + Missing name descriptor + Missing monitor ranges + Detailed block string not properly terminated +EDID block does not conform at all! + Bad year of manufacture + Detailed blocks filled with garbage +I915_WRITE(HTOTAL(pipe), 053f03ff) +I915_WRITE(HBLANK(pipe),0x053f03ff) +I915_WRITE(HSYNC(pipe),0x049f0417) +I915_WRITE(VTOTAL(pipe), 032502ff) +I915_WRITE(VBLANK(pipe),0x032502ff) +I915_WRITE(VSYNC(pipe),0x03080302) +Table has 2247 elements +Change verbosity to 0 +run: return 2246 +Run returns 2247 +gtt_setup: GTT PGETLB_CTL register: 0x0 +gtt_setup: GTT PGETLB_CTL register: 0x1 +gtt_setup: GTT PGETLB_CTL register: 0xbf800001 +gtt_setup: GTT PGETLB_CTL register: 0xbf800003 +gtt_setup is enabled: GTT PGETLB_CTL register: 0x1 +setgtt(0,1600,0xbf800000,4096); +GTT PGETLB_CTL register: 0xbf800001 +GTT Enabled +memset d0020000 to 0x00 for 3145728 bytes +229929 microseconds +PCI: 00:02.0 init 265041 usecs +PCI: 00:02.1 init +PCI: 00:02.1 init 2382 usecs +PCI: 00:1b.0 init +Azalia: codec type: Azalia +Azalia: base = e4440000 +Azalia: codec_mask = 03 +Azalia: Initializing codec #1 +Azalia: codec viddid: 14f12bfa +Azalia: No verb! +Azalia: Initializing codec #0 +Azalia: codec viddid: 11d41981 +Azalia: No verb! +PCI: 00:1b.0 init 25808 usecs +PCI: 00:1c.0 init +Initializing ICH7 PCIe bridge. +PCI: 00:1c.0 init 4490 usecs +PCI: 00:1c.1 init +Initializing ICH7 PCIe bridge. +PCI: 00:1c.1 init 4490 usecs +PCI: 00:1c.2 init +Initializing ICH7 PCIe bridge. +PCI: 00:1c.2 init 4491 usecs +PCI: 00:1c.3 init +Initializing ICH7 PCIe bridge. +PCI: 00:1c.3 init 4489 usecs +PCI: 00:1d.0 init +UHCI: Setting up controller.. done. +PCI: 00:1d.0 init 4925 usecs +PCI: 00:1d.1 init +UHCI: Setting up controller.. done. +PCI: 00:1d.1 init 4926 usecs +PCI: 00:1d.2 init +UHCI: Setting up controller.. done. +PCI: 00:1d.2 init 4924 usecs +PCI: 00:1d.3 init +UHCI: Setting up controller.. done. +PCI: 00:1d.3 init 4925 usecs +PCI: 00:1d.7 init +EHCI: Setting up controller.. done. +PCI: 00:1d.7 init 4933 usecs +PCI: 00:1e.0 init +PCI: 00:1e.0 init 1683 usecs +PCI: 00:1f.0 init +i82801gx: lpc_init +IOAPIC: Initializing IOAPIC at 0xfec00000 +IOAPIC: Bootstrap Processor Local APIC = 0x00 +IOAPIC: ID = 0x02 +IOAPIC: Dumping registers + reg 0x0000: 0x02000000 + reg 0x0001: 0x00170020 + reg 0x0002: 0x00170020 +WARNING: No CMOS option 'power_on_after_fail'. +Set power on after power failure. +NMI sources enabled. +rtc_failed = 0x0 +RTC Init +i8259_configure_irq_trigger: current interrupts are 0x0 +i8259_configure_irq_trigger: try to set interrupts 0x200 +Disabling ACPI via APMC: +done. +Locking SMM. +PCI: 00:1f.0 init 50455 usecs +PCI: 00:1f.1 init +i82801gx_ide: initializing... IDE0 +PCI: 00:1f.1 init 4942 usecs +PCI: 00:1f.2 init +i82801gx_sata: initializing... +SATA controller in AHCI mode. +PCI: 00:1f.2 init 7210 usecs +PCI: 01:00.0 init +PCI: 01:00.0 init 1669 usecs +PCI: 02:00.0 init +PCI: 02:00.0 init 1668 usecs +PCI: 05:00.0 init +Ricoh RL5c476: Initializing. +CF Base = 0 +CF boot not enabled. +PCI: 05:00.0 init 7377 usecs +PCI: 05:00.1 init +PCI: 05:00.1 init 1670 usecs +PCI: 05:00.2 init +PCI: 05:00.2 init 1670 usecs +PCI: 05:00.3 init +PCI: 05:00.3 init 1670 usecs +PNP: 164e.2 init +PNP: 164e.2 init 1582 usecs +PNP: 164e.7 init +PNP: 164e.7 init 1584 usecs +PNP: 164e.19 init +PNP: 164e.19 init 1670 usecs +PNP: 002e.1 init +PNP: 002e.1 init 1582 usecs +PNP: 002e.3 init +PNP: 002e.3 init 1584 usecs +PNP: 002e.7 init +PNP: 002e.7 init 1582 usecs +smbus: PCI: 00:1f.3[0]->I2C: 01:69 init +I2C: 01:69 init 16205 usecs +smbus: PCI: 00:1f.3[0]->I2C: 01:54 init +I2C: 01:54 init 3593 usecs +smbus: PCI: 00:1f.3[0]->I2C: 01:55 init +I2C: 01:55 init 3592 usecs +smbus: PCI: 00:1f.3[0]->I2C: 01:56 init +I2C: 01:56 init 3592 usecs +smbus: PCI: 00:1f.3[0]->I2C: 01:57 init +I2C: 01:57 init 3592 usecs +smbus: PCI: 00:1f.3[0]->I2C: 01:5c init +Locking EEPROM RFID +init EEPROM done +I2C: 01:5c init 28615 usecs +smbus: PCI: 00:1f.3[0]->I2C: 01:5d init +I2C: 01:5d init 3593 usecs +smbus: PCI: 00:1f.3[0]->I2C: 01:5e init +I2C: 01:5e init 3592 usecs +smbus: PCI: 00:1f.3[0]->I2C: 01:5f init +I2C: 01:5f init 3593 usecs +Devices initialized +Show all devs...After init. +Root Device: enabled 1 +CPU_CLUSTER: 0: enabled 1 +APIC: 00: enabled 1 +DOMAIN: 0000: enabled 1 +PCI: 00:00.0: enabled 1 +PCI: 00:02.0: enabled 1 +PCI: 00:02.1: enabled 1 +PCI: 00:1b.0: enabled 1 +PCI: 00:1c.0: enabled 1 +PCI: 00:1c.1: enabled 1 +PCI: 00:1d.0: enabled 1 +PCI: 00:1d.1: enabled 1 +PCI: 00:1d.2: enabled 1 +PCI: 00:1d.3: enabled 1 +PCI: 00:1d.7: enabled 1 +PCI: 00:1f.0: enabled 1 +PNP: 00ff.1: enabled 1 +PNP: 00ff.2: enabled 1 +PNP: 164e.2: enabled 1 +PNP: 164e.3: enabled 0 +PNP: 164e.7: enabled 1 +PNP: 164e.19: enabled 1 +PNP: 002e.0: enabled 0 +PNP: 002e.1: enabled 1 +PNP: 002e.2: enabled 0 +PNP: 002e.3: enabled 1 +PNP: 002e.7: enabled 1 +PNP: 002e.a: enabled 0 +PCI: 00:1f.1: enabled 1 +PCI: 00:1f.2: enabled 1 +PCI: 00:1f.3: enabled 1 +I2C: 01:69: enabled 1 +I2C: 01:54: enabled 1 +I2C: 01:55: enabled 1 +I2C: 01:56: enabled 1 +I2C: 01:57: enabled 1 +I2C: 01:5c: enabled 1 +I2C: 01:5d: enabled 1 +I2C: 01:5e: enabled 1 +I2C: 01:5f: enabled 1 +PCI: 00:1c.2: enabled 1 +PCI: 00:1c.3: enabled 1 +PCI: 00:1e.0: enabled 1 +PCI: 01:00.0: enabled 1 +PCI: 02:00.0: enabled 1 +PCI: 05:00.0: enabled 1 +PCI: 05:00.1: enabled 1 +PCI: 05:00.2: enabled 1 +PCI: 05:00.3: enabled 1 +APIC: 01: enabled 1 +BS: Exiting BS_DEV_INIT state. +BS: BS_DEV_INIT times (us): entry 0 run 1411225 exit 0 +BS: Entering BS_POST_DEVICE state. +CBMEM region bf6d0000-bf7fffff (cbmem_check_toc) +Adding CBMEM entry as no. 4 +Moving GDT to bf6e0600...ok +Finalize devices... +Devices finalized +BS: Exiting BS_POST_DEVICE state. +BS: BS_POST_DEVICE times (us): entry 9470 run 6558 exit 0 +BS: Entering BS_OS_RESUME_CHECK state. +BS: Exiting BS_OS_RESUME_CHECK state. +BS: BS_OS_RESUME_CHECK times (us): entry 0 run 3401 exit 0 +BS: Entering BS_WRITE_TABLES state. +Copying Interrupt Routing Table to 0x000f0000... done. +Adding CBMEM entry as no. 5 +Copying Interrupt Routing Table to 0xbf6e0800... done. +PIRQ table: 272 bytes. +Wrote the mp table end at: 000f0410 - 000f05cc +Adding CBMEM entry as no. 6 +Wrote the mp tabl +6653 bytes lost diff --git a/docs/future/dumps/5927_config b/docs/future/dumps/5927_config @@ -0,0 +1,441 @@ +# +# Automatically generated file; DO NOT EDIT. +# coreboot configuration +# + +# +# General setup +# +CONFIG_EXPERT=y +CONFIG_LOCALVERSION="7BETC7WW (2.08 )" +CONFIG_CBFS_PREFIX="fallback" +CONFIG_COMPILER_GCC=y +# CONFIG_COMPILER_LLVM_CLANG is not set +# CONFIG_ANY_TOOLCHAIN is not set +# CONFIG_CCACHE is not set +# CONFIG_SCONFIG_GENPARSER is not set +CONFIG_USE_OPTION_TABLE=y +CONFIG_COMPRESS_RAMSTAGE=y +CONFIG_INCLUDE_CONFIG_FILE=y +CONFIG_EARLY_CBMEM_INIT=y +# CONFIG_BROKEN_CAR_MIGRATE is not set +# CONFIG_DYNAMIC_CBMEM is not set +# CONFIG_COLLECT_TIMESTAMPS is not set +# CONFIG_USE_BLOBS is not set +# CONFIG_COVERAGE is not set + +# +# Mainboard +# +# CONFIG_VENDOR_AAEON is not set +# CONFIG_VENDOR_ABIT is not set +# CONFIG_VENDOR_ADLINK is not set +# CONFIG_VENDOR_ADVANSUS is not set +# CONFIG_VENDOR_ADVANTECH is not set +# CONFIG_VENDOR_AMD is not set +# CONFIG_VENDOR_AOPEN is not set +# CONFIG_VENDOR_ARIMA is not set +# CONFIG_VENDOR_ARTECGROUP is not set +# CONFIG_VENDOR_ASI is not set +# CONFIG_VENDOR_ASROCK is not set +# CONFIG_VENDOR_ASUS is not set +# CONFIG_VENDOR_A_TREND is not set +# CONFIG_VENDOR_AVALUE is not set +# CONFIG_VENDOR_AXUS is not set +# CONFIG_VENDOR_AZZA is not set +# CONFIG_VENDOR_BACHMANN is not set +# CONFIG_VENDOR_BCOM is not set +# CONFIG_VENDOR_BIFFEROS is not set +# CONFIG_VENDOR_BIOSTAR is not set +# CONFIG_VENDOR_BROADCOM is not set +# CONFIG_VENDOR_COMPAQ is not set +# CONFIG_VENDOR_CUBIETECH is not set +# CONFIG_VENDOR_DIGITALLOGIC is not set +# CONFIG_VENDOR_DMP is not set +# CONFIG_VENDOR_EAGLELION is not set +# CONFIG_VENDOR_ECS is not set +# CONFIG_VENDOR_EMULATION is not set +# CONFIG_VENDOR_GETAC is not set +# CONFIG_VENDOR_GIGABYTE is not set +# CONFIG_VENDOR_GIZMOSPHERE is not set +# CONFIG_VENDOR_GOOGLE is not set +# CONFIG_VENDOR_HP is not set +# CONFIG_VENDOR_IBASE is not set +# CONFIG_VENDOR_IBM is not set +# CONFIG_VENDOR_IEI is not set +# CONFIG_VENDOR_INTEL is not set +# CONFIG_VENDOR_IWAVE is not set +# CONFIG_VENDOR_IWILL is not set +# CONFIG_VENDOR_JETWAY is not set +# CONFIG_VENDOR_KONTRON is not set +# CONFIG_VENDOR_LANNER is not set +CONFIG_VENDOR_LENOVO=y +# CONFIG_VENDOR_LINUTOP is not set +# CONFIG_VENDOR_LIPPERT is not set +# CONFIG_VENDOR_MITAC is not set +# CONFIG_VENDOR_MSI is not set +# CONFIG_VENDOR_NEC is not set +# CONFIG_VENDOR_NEWISYS is not set +# CONFIG_VENDOR_NOKIA is not set +# CONFIG_VENDOR_NVIDIA is not set +# CONFIG_VENDOR_PACKARDBELL is not set +# CONFIG_VENDOR_PCENGINES is not set +# CONFIG_VENDOR_RCA is not set +# CONFIG_VENDOR_RODA is not set +# CONFIG_VENDOR_SAMSUNG is not set +# CONFIG_VENDOR_SIEMENS is not set +# CONFIG_VENDOR_SOYO is not set +# CONFIG_VENDOR_SUNW is not set +# CONFIG_VENDOR_SUPERMICRO is not set +# CONFIG_VENDOR_TECHNEXION is not set +# CONFIG_VENDOR_TECHNOLOGIC is not set +# CONFIG_VENDOR_TELEVIDEO is not set +# CONFIG_VENDOR_TI is not set +# CONFIG_VENDOR_THOMSON is not set +# CONFIG_VENDOR_TRAVERSE is not set +# CONFIG_VENDOR_TYAN is not set +# CONFIG_VENDOR_VIA is not set +# CONFIG_VENDOR_WINENT is not set +# CONFIG_VENDOR_WYSE is not set +CONFIG_BOARD_SPECIFIC_OPTIONS=y +CONFIG_MAINBOARD_DIR="lenovo/x60" +CONFIG_MAINBOARD_PART_NUMBER="ThinkPad X60 / X60s" +CONFIG_IRQ_SLOT_COUNT=18 +CONFIG_MAINBOARD_VENDOR="Lenovo" +CONFIG_MAX_CPUS=2 +CONFIG_RAMTOP=0x200000 +CONFIG_HEAP_SIZE=0x4000 +CONFIG_RAMBASE=0x100000 +CONFIG_VGA_BIOS_ID="8086,27a2" +CONFIG_DRIVERS_PS2_KEYBOARD=y +# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set +# CONFIG_VGA_BIOS is not set +# CONFIG_UDELAY_IO is not set +CONFIG_DCACHE_RAM_BASE=0xffdf8000 +CONFIG_DCACHE_RAM_SIZE=0x8000 +CONFIG_ACPI_SSDTX_NUM=0 +# CONFIG_PCI_64BIT_PREF_MEM is not set +CONFIG_MMCONF_BASE_ADDRESS=0xf0000000 +CONFIG_UART_FOR_CONSOLE=0 +CONFIG_ID_SECTION_OFFSET=0x80 +CONFIG_STACK_SIZE=0x1000 +CONFIG_CACHE_ROM_SIZE_OVERRIDE=0 +CONFIG_CBFS_SIZE=0x200000 +CONFIG_BOARD_LENOVO_X60=y +# CONFIG_BOARD_LENOVO_X201 is not set +# CONFIG_BOARD_LENOVO_X230 is not set +# CONFIG_BOARD_LENOVO_T520 is not set +# CONFIG_BOARD_LENOVO_T530 is not set +# CONFIG_BOARD_LENOVO_T60 is not set +CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="LENOVO" +CONFIG_SEABIOS_PS2_TIMEOUT=3000 +CONFIG_MAINBOARD_VERSION="ThinkPad X60" +CONFIG_CPU_ADDR_BITS=32 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 +# CONFIG_USBDEBUG is not set +CONFIG_MAXIMUM_SUPPORTED_FREQUENCY=0 +CONFIG_BOARD_ROMSIZE_KB_2048=y +# CONFIG_COREBOOT_ROMSIZE_KB_64 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_128 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set +CONFIG_COREBOOT_ROMSIZE_KB_2048=y +# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_8192 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set +CONFIG_COREBOOT_ROMSIZE_KB=2048 +CONFIG_ROM_SIZE=0x200000 +CONFIG_MAINBOARD_SERIAL_NUMBER="L3AZ921" +CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="1703WMF" +CONFIG_ARCH_X86=y +# CONFIG_ARCH_ARMV7 is not set +CONFIG_ARCH_BOOTBLOCK_X86_32=y +CONFIG_ARCH_ROMSTAGE_X86_32=y +CONFIG_ARCH_RAMSTAGE_X86_32=y +CONFIG_AP_IN_SIPI_WAIT=y +# CONFIG_SIPI_VECTOR_IN_ROM is not set +CONFIG_NUM_IPI_STARTS=2 +# CONFIG_ROMCC is not set +CONFIG_PC80_SYSTEM=y +CONFIG_BOOTBLOCK_NORTHBRIDGE_INIT="northbridge/intel/i945/bootblock.c" +CONFIG_HAVE_CMOS_DEFAULT=y +CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default" +CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT="southbridge/intel/i82801gx/bootblock.c" +CONFIG_IOAPIC_INTERRUPTS_ON_FSB=y +# CONFIG_IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS is not set +CONFIG_HPET_ADDRESS=0xfed00000 +# CONFIG_ARCH_BOOTBLOCK_ARMV7 is not set +# CONFIG_ARCH_ROMSTAGE_ARMV7 is not set +# CONFIG_ARCH_RAMSTAGE_ARMV7 is not set +# CONFIG_MAINBOARD_HAS_CHROMEOS is not set +CONFIG_BOOTBLOCK_SIMPLE=y +# CONFIG_BOOTBLOCK_NORMAL is not set +CONFIG_BOOTBLOCK_SOURCE="bootblock_simple.c" +# CONFIG_UPDATE_IMAGE is not set + +# +# Chipset +# + +# +# CPU +# +# CONFIG_CPU_ALLWINNER_A10 is not set +# CONFIG_CPU_ARMLTD_CORTEX_A9 is not set +# CONFIG_CPU_SAMSUNG_EXYNOS5250 is not set +# CONFIG_CPU_SAMSUNG_EXYNOS5420 is not set +# CONFIG_CPU_TI_AM335X is not set +CONFIG_SOCKET_SPECIFIC_OPTIONS=y +CONFIG_XIP_ROM_SIZE=0x10000 +# CONFIG_CPU_AMD_AGESA is not set +CONFIG_HIGH_SCRATCH_MEMORY_SIZE=0x0 +CONFIG_CPU_INTEL_MODEL_6EX=y +CONFIG_CPU_INTEL_MODEL_6FX=y +CONFIG_SMM_TSEG_SIZE=0 +CONFIG_CPU_INTEL_SOCKET_MFCPGA478=y +CONFIG_SSE2=y +# CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE is not set +# CONFIG_CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED is not set +# CONFIG_PARALLEL_CPU_INIT is not set +CONFIG_UDELAY_LAPIC=y +CONFIG_LAPIC_MONOTONIC_TIMER=y +# CONFIG_UDELAY_TSC is not set +# CONFIG_UDELAY_TIMER2 is not set +# CONFIG_TSC_CALIBRATE_WITH_IO is not set +# CONFIG_TSC_SYNC_LFENCE is not set +CONFIG_TSC_SYNC_MFENCE=y +CONFIG_LOGICAL_CPUS=y +# CONFIG_SMM_TSEG is not set +# CONFIG_SMM_MODULES is not set +# CONFIG_X86_AMD_FIXED_MTRRS is not set +# CONFIG_PLATFORM_USES_FSP is not set +# CONFIG_PARALLEL_MP is not set +# CONFIG_BACKUP_DEFAULT_SMM_REGION is not set +# CONFIG_MIRROR_PAYLOAD_TO_RAM_BEFORE_LOADING is not set +CONFIG_CACHE_AS_RAM=y +CONFIG_SMP=y +CONFIG_AP_SIPI_VECTOR=0xfffff000 +CONFIG_MMX=y +CONFIG_SSE=y +CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y +CONFIG_CPU_MICROCODE_ADDED_DURING_BUILD=y +CONFIG_CPU_MICROCODE_CBFS_GENERATE=y +# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL is not set +# CONFIG_CPU_MICROCODE_CBFS_NONE is not set + +# +# Northbridge +# +CONFIG_VIDEO_MB=0 +# CONFIG_NORTHBRIDGE_AMD_AGESA is not set +# CONFIG_AMD_NB_CIMX is not set +# CONFIG_NORTHBRIDGE_AMD_CIMX_RD890 is not set +CONFIG_NORTHBRIDGE_SPECIFIC_OPTIONS=y +CONFIG_NORTHBRIDGE_INTEL_I945=y +# CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GC is not set +CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM=y +CONFIG_CHANNEL_XOR_RANDOMIZATION=y +# CONFIG_OVERRIDE_CLOCK_DISABLE is not set +# CONFIG_CHECK_SLFRCS_ON_RESUME is not set +CONFIG_HPET_MIN_TICKS=0x80 +CONFIG_MAX_PIRQ_LINKS=4 + +# +# Southbridge +# +CONFIG_EHCI_BAR=0xfef00000 +# CONFIG_AMD_SB_CIMX is not set +# CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800 is not set +# CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900 is not set +CONFIG_SOUTHBRIDGE_INTEL_COMMON=y +CONFIG_SOUTHBRIDGE_INTEL_I82801GX=y +CONFIG_SOUTHBRIDGE_RICOH_RL5C476=y + +# +# Super I/O +# +CONFIG_SUPERIO_NSC_PC87382=y +CONFIG_SUPERIO_NSC_PC87392=y + +# +# Embedded Controllers +# +CONFIG_EC_ACPI=y +CONFIG_EC_LENOVO_H8=y +CONFIG_H8_DOCK_EARLY_INIT=y +CONFIG_EC_LENOVO_PMH7=y + +# +# SoC +# + +# +# Devices +# +CONFIG_MAINBOARD_HAS_NATIVE_VGA_INIT=y +# CONFIG_MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG is not set +CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT=y +# CONFIG_VGA_ROM_RUN is not set +# CONFIG_ON_DEVICE_ROM_RUN is not set +# CONFIG_MULTIPLE_VGA_ADAPTERS is not set +CONFIG_PCI=y +# CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT is not set +CONFIG_PCIX_PLUGIN_SUPPORT=y +CONFIG_PCIEXP_PLUGIN_SUPPORT=y +CONFIG_AGP_PLUGIN_SUPPORT=y +CONFIG_CARDBUS_PLUGIN_SUPPORT=y +# CONFIG_AZALIA_PLUGIN_SUPPORT is not set +# CONFIG_PCIEXP_COMMON_CLOCK is not set +# CONFIG_PCIEXP_ASPM is not set +CONFIG_PCI_BUS_SEGN_BITS=0 +# CONFIG_EARLY_PCI_BRIDGE is not set + +# +# VGA BIOS +# + +# +# Display +# + +# +# PXE ROM +# +# CONFIG_PXE_ROM is not set +CONFIG_SUBSYSTEM_VENDOR_ID=0x0000 +CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 + +# +# Generic Drivers +# +# CONFIG_DRIVERS_I2C_RTD2132 is not set +CONFIG_DRIVERS_ICS_954309=y +# CONFIG_INTEL_DP is not set +# CONFIG_INTEL_DDI is not set +# CONFIG_INTEL_EDID is not set +# CONFIG_IPMI_KCS is not set +# CONFIG_DRIVER_MAXIM_MAX77686 is not set +# CONFIG_DRIVER_PARADE_PS8625 is not set +# CONFIG_TPM is not set +# CONFIG_DRIVERS_SIL_3114 is not set +# CONFIG_SPI_FLASH is not set +# CONFIG_DRIVER_TI_TPS65090 is not set +CONFIG_DRIVERS_UART=y +CONFIG_DRIVERS_UART_8250IO=y +# CONFIG_NO_UART_ON_SUPERIO is not set +# CONFIG_DRIVERS_UART_8250MEM is not set +# CONFIG_HAVE_UART_SPECIAL is not set +# CONFIG_DRIVERS_UART_OXPCIE is not set +# CONFIG_DRIVERS_UART_PL011 is not set +CONFIG_HAVE_USBDEBUG=y +# CONFIG_HAVE_USBDEBUG_OPTIONS is not set +# CONFIG_DRIVER_XPOWERS_AXP209 is not set +CONFIG_MMCONF_SUPPORT_DEFAULT=y +CONFIG_MMCONF_SUPPORT=y +# CONFIG_BOOTMODE_STRAPS is not set + +# +# Console +# +CONFIG_SQUELCH_EARLY_SMP=y +CONFIG_CONSOLE_SERIAL=y + +# +# I/O mapped, 8250-compatible +# +CONFIG_TTYS0_BASE=0x3f8 +CONFIG_CONSOLE_SERIAL_115200=y +# CONFIG_CONSOLE_SERIAL_57600 is not set +# CONFIG_CONSOLE_SERIAL_38400 is not set +# CONFIG_CONSOLE_SERIAL_19200 is not set +# CONFIG_CONSOLE_SERIAL_9600 is not set +CONFIG_TTYS0_BAUD=115200 +CONFIG_TTYS0_LCS=3 +# CONFIG_SPKMODEM is not set +# CONFIG_CONSOLE_NE2K is not set +CONFIG_CONSOLE_CBMEM=y +CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x10000 +CONFIG_CONSOLE_CAR_BUFFER_SIZE=0xc00 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8=y +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set +# CONFIG_NO_POST is not set +# CONFIG_CMOS_POST is not set +# CONFIG_POST_IO is not set +CONFIG_POST_DEVICE=y +CONFIG_POST_DEVICE_NONE=y +# CONFIG_POST_DEVICE_LPC is not set +# CONFIG_POST_DEVICE_PCI_PCIE is not set +CONFIG_HAVE_ACPI_RESUME=y +# CONFIG_HAVE_ACPI_SLIC is not set +CONFIG_HAVE_HARD_RESET=y +CONFIG_HAVE_MONOTONIC_TIMER=y +# CONFIG_TIMER_QUEUE is not set +CONFIG_HAVE_OPTION_TABLE=y +# CONFIG_PIRQ_ROUTE is not set +CONFIG_HAVE_SMI_HANDLER=y +# CONFIG_PCI_IO_CFG_EXT is not set +CONFIG_IOAPIC=y +CONFIG_USE_WATCHDOG_ON_BOOT=y +# CONFIG_VGA is not set +# CONFIG_GFXUMA is not set +# CONFIG_RELOCATABLE_MODULES is not set +# CONFIG_HAVE_REFCODE_BLOB is not set +CONFIG_HAVE_ACPI_TABLES=y +CONFIG_HAVE_MP_TABLE=y +CONFIG_HAVE_PIRQ_TABLE=y + +# +# System tables +# +CONFIG_GENERATE_ACPI_TABLES=y +CONFIG_GENERATE_MP_TABLE=y +CONFIG_GENERATE_PIRQ_TABLE=y +CONFIG_GENERATE_SMBIOS_TABLES=y + +# +# Payload +# +# CONFIG_PAYLOAD_NONE is not set +CONFIG_PAYLOAD_ELF=y +# CONFIG_PAYLOAD_LINUX is not set +# CONFIG_PAYLOAD_SEABIOS is not set +# CONFIG_PAYLOAD_FILO is not set +# CONFIG_PAYLOAD_GRUB2 is not set +# CONFIG_PAYLOAD_TIANOCORE is not set +# CONFIG_SEABIOS_THREAD_OPTIONROMS is not set +CONFIG_PAYLOAD_FILE="grub.elf" +CONFIG_COMPRESSED_PAYLOAD_LZMA=y + +# +# Debugging +# +# CONFIG_GDB_STUB is not set +# CONFIG_DEBUG_CBFS is not set +CONFIG_HAVE_DEBUG_RAM_SETUP=y +# CONFIG_DEBUG_RAM_SETUP is not set +# CONFIG_HAVE_DEBUG_CAR is not set +# CONFIG_DEBUG_PIRQ is not set +# CONFIG_HAVE_DEBUG_SMBUS is not set +# CONFIG_DEBUG_SMI is not set +# CONFIG_DEBUG_SMM_RELOCATION is not set +# CONFIG_DEBUG_MALLOC is not set +# CONFIG_DEBUG_ACPI is not set +# CONFIG_TRACE is not set +# CONFIG_ENABLE_APIC_EXT_ID is not set +CONFIG_WARNINGS_ARE_ERRORS=y +# CONFIG_POWER_BUTTON_DEFAULT_ENABLE is not set +# CONFIG_POWER_BUTTON_DEFAULT_DISABLE is not set +# CONFIG_POWER_BUTTON_FORCE_ENABLE is not set +# CONFIG_POWER_BUTTON_FORCE_DISABLE is not set +# CONFIG_POWER_BUTTON_IS_OPTIONAL is not set +CONFIG_REG_SCRIPT=y +CONFIG_MAX_REBOOT_CNT=3 diff --git a/docs/future/dumps/5927_crashdump b/docs/future/dumps/5927_crashdump @@ -0,0 +1,77 @@ +Time: 1401830541 s 274954 us +Kernel: 3.14.4-gnuowen +PCI ID: 0x27a2 +EIR: 0x00000010 +IER: 0x00028053 +PGTBL_ER: 0x00000013 +FORCEWAKE: 0x00000000 +DERRMR: 0x00000000 +CCID: 0x00000000 +Missed interrupts: 0x00000000 + fence[0] = 00000000 + fence[1] = 00000000 + fence[2] = 00000000 + fence[3] = 00000000 + fence[4] = 00000000 + fence[5] = 00000000 + fence[6] = 00000000 + fence[7] = 00000000 + fence[8] = 00000000 + fence[9] = 00000000 + fence[10] = 00000000 + fence[11] = 00000000 + fence[12] = 00000000 + fence[13] = 00000000 + fence[14] = 00000000 + fence[15] = 00000000 + INSTDONE_0: 0x7fffffc0 + INSTDONE_1: 0x00000000 + INSTDONE_2: 0x00000000 + INSTDONE_3: 0x00000000 +Active [0]: +Pinned [0]: +Num Pipes: 2 +Pipe [0]: + Power: off + SRC: 00000000 +Plane [0]: + CNTR: 00000000 + STRIDE: 00000000 + SIZE: 00000000 + POS: 00000000 + ADDR: 00000000 +Cursor [0]: + CNTR: 00000000 + POS: 00000000 + BASE: 00000000 +Pipe [1]: + Power: off + SRC: 00000000 +Plane [1]: + CNTR: 00000000 + STRIDE: 00000000 + SIZE: 00000000 + POS: 00000000 + ADDR: 00000000 +Cursor [1]: + CNTR: 00000000 + POS: 00000000 + BASE: 00000000 +CPU transcoder: A + Power: off + CONF: 00000000 + HTOTAL: 00000000 + HBLANK: 00000000 + HSYNC: 00000000 + VTOTAL: 00000000 + VBLANK: 00000000 + VSYNC: 00000000 +CPU transcoder: A + Power: off + CONF: 00000000 + HTOTAL: 00000000 + HBLANK: 00000000 + HSYNC: 00000000 + VTOTAL: 00000000 + VBLANK: 00000000 + VSYNC: 00000000 diff --git a/docs/future/dumps/coreboot_5296_oprom_grub_cbmemc b/docs/future/dumps/coreboot_5296_oprom_grub_cbmemc @@ -0,0 +1,1436 @@ + + +coreboot-4.0-6195-g3b7c130-7BETC7WW (2.08 ) Tue Jun 3 16:36:44 BST 2014 starting... + +Mobile Intel(R) 82945GM/GME Express Chipset +(G)MCH capable of up to FSB 800 MHz +(G)MCH capable of up to DDR2-667 +Setting up static southbridge registers... GPIOS... done. +Disabling Watchdog reboot... done. +Setting up static northbridge registers... done. +Waiting for MCHBAR to come up...ok +PM1_CNT: 00001c00 +SMBus controller enabled. +Setting up RAM controller. +This mainboard supports Dual Channel Operation. +DDR II Channel 0 Socket 0: x16DS +DDR II Channel 1 Socket 0: x8DDS +Memory will be driven at 667MHz with CAS=5 clocks +tRAS = 15 cycles +tRP = 5 cycles +tRCD = 5 cycles +Refresh: 7.8us +tWR = 5 cycles +DIMM 0 side 0 = 512 MB +DIMM 0 side 1 = 512 MB +DIMM 2 side 0 = 1024 MB +DIMM 2 side 1 = 1024 MB +tRFC = 43 cycles +Setting Graphics Frequency... +FSB: 667 MHz Voltage: 1.05V Render: 250Mhz Display: 200MHz +Setting Memory Frequency... CLKCFG=0x00010023, CLKCFG=0x00010043, ok +Setting mode of operation for memory channels...Dual Channel Assymetric. +Programming Clock Crossing...MEM=667 FSB=667... ok +Setting RAM size... +C0DRB = 0x20202010 +C1DRB = 0x60606040 +TOLUD = 0x00c0 +Setting row attributes... +C0DRA = 0x0033 +C1DRA = 0x0033 +DIMM0 has 8 banks. +DIMM2 has 8 banks. +one dimm per channel config.. +Initializing System Memory IO... +Programming Dual Channel RCOMP +Table Index: 3 +Programming DLL Timings... +Enabling System Memory IO... +jedec enable sequence: bank 0 +jedec enable sequence: bank 1 +bankaddr from bank size of rank 0 +jedec enable sequence: bank 4 +bankaddr from bank size of rank 1 +jedec enable sequence: bank 5 +bankaddr from bank size of rank 4 +receive_enable_autoconfig() for channel 0 + find_strobes_low() + set_receive_enable() medium=0x3, coarse=0x5 + set_receive_enable() medium=0x1, coarse=0x5 + find_strobes_edge() + set_receive_enable() medium=0x1, coarse=0x5 + set_receive_enable() medium=0x3, coarse=0x5 + set_receive_enable() medium=0x1, coarse=0x5 + add_quarter_clock() mediumcoarse=15 fine=f3 + set_receive_enable() medium=0x3, coarse=0x5 + find_preamble() + set_receive_enable() medium=0x3, coarse=0x4 + set_receive_enable() medium=0x3, coarse=0x3 + add_quarter_clock() mediumcoarse=0f fine=73 + normalize() + set_receive_enable() medium=0x0, coarse=0x4 +receive_enable_autoconfig() for channel 1 + find_strobes_low() + set_receive_enable() medium=0x3, coarse=0x5 + set_receive_enable() medium=0x1, coarse=0x5 + find_strobes_edge() + set_receive_enable() medium=0x1, coarse=0x5 + add_quarter_clock() mediumcoarse=15 fine=c5 + set_receive_enable() medium=0x3, coarse=0x5 + find_preamble() + set_receive_enable() medium=0x3, coarse=0x4 + set_receive_enable() medium=0x3, coarse=0x3 + add_quarter_clock() mediumcoarse=0f fine=45 + normalize() + set_receive_enable() medium=0x0, coarse=0x4 +RAM initialization finished. +Setting up Egress Port RCRB +Loading p + +*** Log truncated, 497 characters dropped. *** + +Adding CBMEM entry as no. 3 +Trying CBFS ramstage loader. +CBFS: loading stage fallback/ramstage @ 0x100000 (327736 bytes), entry @ 0x100000 +coreboot-4.0-6195-g3b7c130-7BETC7WW (2.08 ) Tue Jun 3 16:36:44 BST 2014 booting... +BS: Entering BS_PRE_DEVICE state. +BS: Exiting BS_PRE_DEVICE state. +BS: BS_PRE_DEVICE times (us): entry 0 run 2976 exit 0 +BS: Entering BS_DEV_INIT_CHIPS state. +BS: Exiting BS_DEV_INIT_CHIPS state. +BS: BS_DEV_INIT_CHIPS times (us): entry 0 run 3323 exit 0 +BS: Entering BS_DEV_ENUMERATE state. +Enumerating buses... +Show all devs...Before device enumeration. +Root Device: enabled 1 +CPU_CLUSTER: 0: enabled 1 +APIC: 00: enabled 1 +DOMAIN: 0000: enabled 1 +PCI: 00:00.0: enabled 1 +PCI: 00:02.0: enabled 1 +PCI: 00:02.1: enabled 1 +PCI: 00:1b.0: enabled 1 +PCI: 00:1c.0: enabled 1 +PCI: 00:1c.1: enabled 1 +PCI: 00:1d.0: enabled 1 +PCI: 00:1d.1: enabled 1 +PCI: 00:1d.2: enabled 1 +PCI: 00:1d.3: enabled 1 +PCI: 00:1d.7: enabled 1 +PCI: 00:1f.0: enabled 1 +PNP: 00ff.1: enabled 1 +PNP: 00ff.2: enabled 1 +PNP: 164e.2: enabled 1 +PNP: 164e.3: enabled 0 +PNP: 164e.7: enabled 1 +PNP: 164e.19: enabled 1 +PNP: 002e.0: enabled 0 +PNP: 002e.1: enabled 1 +PNP: 002e.2: enabled 0 +PNP: 002e.3: enabled 1 +PNP: 002e.7: enabled 1 +PNP: 002e.a: enabled 0 +PCI: 00:1f.1: enabled 1 +PCI: 00:1f.2: enabled 1 +PCI: 00:1f.3: enabled 1 +I2C: 00:69: enabled 1 +I2C: 00:54: enabled 1 +I2C: 00:55: enabled 1 +I2C: 00:56: enabled 1 +I2C: 00:57: enabled 1 +I2C: 00:5c: enabled 1 +I2C: 00:5d: enabled 1 +I2C: 00:5e: enabled 1 +I2C: 00:5f: enabled 1 +Compare with tree... +Root Device: enabled 1 + CPU_CLUSTER: 0: enabled 1 + APIC: 00: enabled 1 + DOMAIN: 0000: enabled 1 + PCI: 00:00.0: enabled 1 + PCI: 00:02.0: enabled 1 + PCI: 00:02.1: enabled 1 + PCI: 00:1b.0: enabled 1 + PCI: 00:1c.0: enabled 1 + PCI: 00:1c.1: enabled 1 + PCI: 00:1d.0: enabled 1 + PCI: 00:1d.1: enabled 1 + PCI: 00:1d.2: enabled 1 + PCI: 00:1d.3: enabled 1 + PCI: 00:1d.7: enabled 1 + PCI: 00:1f.0: enabled 1 + PNP: 00ff.1: enabled 1 + PNP: 00ff.2: enabled 1 + PNP: 164e.2: enabled 1 + PNP: 164e.3: enabled 0 + PNP: 164e.7: enabled 1 + PNP: 164e.19: enabled 1 + PNP: 002e.0: enabled 0 + PNP: 002e.1: enabled 1 + PNP: 002e.2: enabled 0 + PNP: 002e.3: enabled 1 + PNP: 002e.7: enabled 1 + PNP: 002e.a: enabled 0 + PCI: 00:1f.1: enabled 1 + PCI: 00:1f.2: enabled 1 + PCI: 00:1f.3: enabled 1 + I2C: 00:69: enabled 1 + I2C: 00:54: enabled 1 + I2C: 00:55: enabled 1 + I2C: 00:56: enabled 1 + I2C: 00:57: enabled 1 + I2C: 00:5c: enabled 1 + I2C: 00:5d: enabled 1 + I2C: 00:5e: enabled 1 + I2C: 00:5f: enabled 1 +scan_static_bus for Root Device +CPU_CLUSTER: 0 enabled +DOMAIN: 0000 enabled +DOMAIN: 0000 scanning... +PCI: pci_scan_bus for bus 00 +PCI: 00:00.0 [8086/27a0] ops +PCI: 00:00.0 [8086/27a0] enabled +PCI: 00:02.0 [8086/27a2] ops +PCI: 00:02.0 [8086/27a2] enabled +PCI: 00:02.1 [8086/27a6] ops +PCI: 00:02.1 [8086/27a6] enabled +PCI: 00:1b.0 [8086/27d8] ops +PCI: 00:1b.0 [8086/27d8] enabled +PCI: 00:1c.0 [8086/0000] bus ops +PCI: 00:1c.0 [8086/27d0] enabled +PCI: 00:1c.1 [8086/0000] bus ops +PCI: 00:1c.1 [8086/27d2] enabled +PCI: 00:1c.2 [8086/0000] bus ops +PCI: 00:1c.2 [8086/27d4] enabled +PCI: 00:1c.3 [8086/0000] bus ops +PCI: 00:1c.3 [8086/27d6] enabled +PCI: 00:1d.0 [8086/27c8] ops +PCI: 00:1d.0 [8086/27c8] enabled +PCI: 00:1d.1 [8086/27c9] ops +PCI: 00:1d.1 [8086/27c9] enabled +PCI: 00:1d.2 [8086/27ca] ops +PCI: 00:1d.2 [8086/27ca] enabled +PCI: 00:1d.3 [8086/27cb] ops +PCI: 00:1d.3 [8086/27cb] enabled +PCI: 00:1d.7 [8086/27cc] ops +PCI: 00:1d.7 [8086/27cc] enabled +PCI: 00:1e.0 [8086/2448] bus ops +PCI: 00:1e.0 [8086/2448] enabled +PCI: 00:1f.0 [8086/27b9] bus ops +PCI: 00:1f.0 [8086/27b9] enabled +PCI: 00:1f.1 [8086/27df] ops +PCI: 00:1f.1 [8086/27df] enabled +PCI: 00:1f.2 [8086/0000] ops +PCI: 00:1f.2 [8086/27c4] enabled +PCI: 00:1f.3 [8086/27da] bus ops +PCI: 00:1f.3 [8086/27da] enabled +do_pci_scan_bridge for PCI: 00:1c.0 +PCI: pci_scan_bus for bus 01 +PCI: 01:00.0 [8086/109a] enabled +PCI: pci_scan_bus returning with max=001 +do_pci_scan_bridge returns max 1 +do_pci_scan_bridge for PCI: 00:1c.1 +PCI: pci_scan_bus for bus 02 +PCI: 02:00.0 [168c/002b] enabled +PCI: pci_scan_bus returning with max=002 +do_pci_scan_bridge returns max 2 +do_pci_scan_bridge for PCI: 00:1c.2 +PCI: pci_scan_bus for bus 03 +PCI: pci_scan_bus returning with max=003 +do_pci_scan_bridge returns max 3 +do_pci_scan_bridge for PCI: 00:1c.3 +PCI: pci_scan_bus for bus 04 +PCI: pci_scan_bus returning with max=004 +do_pci_scan_bridge returns max 4 +do_pci_scan_bridge for PCI: 00:1e.0 +PCI: pci_scan_bus for bus 05 +PCI: 05:00.0 [1180/0476] bus ops +PCI: 05:00.0 [1180/0476] enabled +PCI: 05:00.1 [1180/0552] enabled +PCI: 05:00.2 [1180/0822] enabled +PCI: 05:00.3 [1180/0843] enabled +do_pci_scan_bridge for PCI: 05:00.0 +PCI: pci_scan_bus for bus 06 +PCI: pci_scan_bus returning with max=006 +do_pci_scan_bridge returns max 6 +PCI: pci_scan_bus returning with max=006 +do_pci_scan_bridge returns max 6 +scan_static_bus for PCI: 00:1f.0 +WARNING: No CMOS option 'touchpad'. +PNP: 00ff.1 enabled +recv_ec_data: 0x37 +recv_ec_data: 0x42 +recv_ec_data: 0x48 +recv_ec_data: 0x54 +recv_ec_data: 0x33 +recv_ec_data: 0x37 +recv_ec_data: 0x57 +recv_ec_data: 0x57 +recv_ec_data: 0x04 +recv_ec_data: 0x03 +recv_ec_data: 0x00 +recv_ec_data: 0x11 +EC Firmware ID 7BHT37WW-3.4, Version 0.01B +recv_ec_data: 0x00 +recv_ec_data: 0x10 +recv_ec_data: 0x20 +recv_ec_data: 0x30 +recv_ec_data: 0x00 +recv_ec_data: 0xa6 +recv_ec_data: 0x01 +recv_ec_data: 0x30 +PNP: 00ff.2 enabled +PNP: 164e.2 enabled +PNP: 164e.3 disabled +PNP: 164e.7 enabled +PNP: 164e.19 enabled +PNP: 002e.0 disabled +PNP: 002e.1 enabled +PNP: 002e.2 disabled +PNP: 002e.3 enabled +PNP: 002e.7 enabled +PNP: 002e.a disabled +scan_static_bus for PCI: 00:1f.0 done +scan_static_bus for PCI: 00:1f.3 +smbus: PCI: 00:1f.3[0]->I2C: 01:69 enabled +smbus: PCI: 00:1f.3[0]->I2C: 01:54 enabled +smbus: PCI: 00:1f.3[0]->I2C: 01:55 enabled +smbus: PCI: 00:1f.3[0]->I2C: 01:56 enabled +smbus: PCI: 00:1f.3[0]->I2C: 01:57 enabled +smbus: PCI: 00:1f.3[0]->I2C: 01:5c enabled +smbus: PCI: 00:1f.3[0]->I2C: 01:5d enabled +smbus: PCI: 00:1f.3[0]->I2C: 01:5e enabled +smbus: PCI: 00:1f.3[0]->I2C: 01:5f enabled +scan_static_bus for PCI: 00:1f.3 done +PCI: pci_scan_bus returning with max=006 +scan_static_bus for Root Device done +done +BS: Exiting BS_DEV_ENUMERATE state. +BS: BS_DEV_ENUMERATE times (us): entry 0 run 529959 exit 0 +BS: Entering BS_DEV_RESOURCES state. +found VGA at PCI: 00:02.0 +Setting up VGA for PCI: 00:02.0 +Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000 +Setting PCI_BRIDGE_CTL_VGA for bridge Root Device +Allocating resources... +Reading resources... +Root Device read_resources bus 0 link: 0 +CPU_CLUSTER: 0 read_resources bus 0 link: 0 +APIC: 00 missing read_resources +CPU_CLUSTER: 0 read_resources bus 0 link: 0 done +DOMAIN: 0000 read_resources bus 0 link: 0 +Adding PCIe enhanced config space BAR 0xf0000000-0xf4000000. +PCI: 00:1c.0 read_resources bus 1 link: 0 +PCI: 00:1c.0 read_resources bus 1 link: 0 done +PCI: 00:1c.1 read_resources bus 2 link: 0 +PCI: 00:1c.1 read_resources bus 2 link: 0 done +PCI: 00:1c.2 read_resources bus 3 link: 0 +PCI: 00:1c.2 read_resources bus 3 link: 0 done +PCI: 00:1c.3 read_resources bus 4 link: 0 +PCI: 00:1c.3 read_resources bus 4 link: 0 done +PCI: 00:1e.0 read_resources bus 5 link: 0 +PCI: 05:00.0 read_resources bus 6 link: 0 +PCI: 05:00.0 read_resources bus 6 link: 0 done +PCI: 00:1e.0 read_resources bus 5 link: 0 done +PCI: 00:1f.0 read_resources bus 0 link: 0 +PNP: 00ff.1 missing read_resources +PNP: 00ff.2 missing read_resources +PCI: 00:1f.0 read_resources bus 0 link: 0 done +PCI: 00:1f.3 read_resources bus 1 link: 0 +PCI: 00:1f.3 read_resources bus 1 link: 0 done +DOMAIN: 0000 read_resources bus 0 link: 0 done +Root Device read_resources bus 0 link: 0 done +Done reading resources. +Show resources in subtree (Root Device)...After reading. + Root Device child on link 0 CPU_CLUSTER: 0 + CPU_CLUSTER: 0 child on link 0 APIC: 00 + APIC: 00 + DOMAIN: 0000 child on link 0 PCI: 00:00.0 + DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000 + DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffffffff flags 40040200 index 10000100 + PCI: 00:00.0 + PCI: 00:00.0 resource base f0000000 size 4000000 align 0 gran 0 limit 0 flags e0000200 index cf + PCI: 00:02.0 + PCI: 00:02.0 resource base 0 size 80000 align 19 gran 19 limit ffffffff flags 200 index 10 + PCI: 00:02.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 14 + PCI: 00:02.0 resource base 0 size 10000000 align 28 gran 28 limit ffffffff flags 1200 index 18 + PCI: 00:02.0 resource base 0 size 40000 align 18 gran 18 limit ffffffff flags 200 index 1c + PCI: 00:02.1 + PCI: 00:02.1 resource base 0 size 80000 align 19 gran 19 limit ffffffff flags 200 index 10 + PCI: 00:1b.0 + PCI: 00:1b.0 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10 + PCI: 00:1c.0 child on link 0 PCI: 01:00.0 + PCI: 00:1c.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c + PCI: 00:1c.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 + PCI: 00:1c.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 + PCI: 01:00.0 + PCI: 01:00.0 resource base 0 size 20000 align 17 gran 17 limit ffffffff flags 200 index 10 + PCI: 01:00.0 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 18 + PCI: 00:1c.1 child on link 0 PCI: 02:00.0 + PCI: 00:1c.1 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c + PCI: 00:1c.1 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 + PCI: 00:1c.1 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 + PCI: 02:00.0 + PCI: 02:00.0 resource base 0 size 10000 align 16 gran 16 limit ffffffffffffffff flags 201 index 10 + PCI: 00:1c.2 + PCI: 00:1c.2 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c + PCI: 00:1c.2 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 + PCI: 00:1c.2 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 + PCI: 00:1c.3 + PCI: 00:1c.3 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c + PCI: 00:1c.3 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 + PCI: 00:1c.3 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 + PCI: 00:1d.0 + PCI: 00:1d.0 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 20 + PCI: 00:1d.1 + PCI: 00:1d.1 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 20 + PCI: 00:1d.2 + PCI: 00:1d.2 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 20 + PCI: 00:1d.3 + PCI: 00:1d.3 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 20 + PCI: 00:1d.7 + PCI: 00:1d.7 resource base 0 size 400 align 10 gran 10 limit ffffffff flags 200 index 10 + PCI: 00:1e.0 child on link 0 PCI: 05:00.0 + PCI: 00:1e.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c + PCI: 00:1e.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 + PCI: 00:1e.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 + PCI: 05:00.0 + PCI: 05:00.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10 + PCI: 05:00.0 resource base 0 size 1000 align 2 gran 2 limit ffffffff flags 100 index 2c + PCI: 05:00.0 resource base 0 size 1000 align 2 gran 2 limit ffffffff flags 100 index 34 + PCI: 05:00.0 resource base 0 size 2000000 align 12 gran 12 limit ffffffff flags 1200 index 1c + PCI: 05:00.0 resource base 0 size 2000000 align 12 gran 12 limit ffffffff flags 200 index 24 + PCI: 05:00.1 + PCI: 05:00.1 resource base 0 size 800 align 11 gran 11 limit ffffffff flags 200 index 10 + PCI: 05:00.2 + PCI: 05:00.2 resource base 0 size 100 align 8 gran 8 limit ffffffff flags 200 index 10 + PCI: 05:00.3 + PCI: 05:00.3 resource base 0 size 100 align 8 gran 8 limit ffffffff flags 200 index 10 + PCI: 00:1f.0 child on link 0 PNP: 00ff.1 + PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000 + PCI: 00:1f.0 resource base ff800000 size 800000 align 0 gran 0 limit 0 flags c0040200 index 10000100 + PCI: 00:1f.0 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3 + PNP: 00ff.1 + PNP: 00ff.1 resource base 15e0 size 10 align 5 gran 5 limit 0 flags 80000100 index 77 + PNP: 00ff.2 + PNP: 00ff.2 resource base 62 size 0 align 0 gran 0 limit 0 flags c0000100 index 60 + PNP: 00ff.2 resource base 66 size 0 align 0 gran 0 limit 0 flags c0000100 index 62 + PNP: 00ff.2 resource base 1600 size 0 align 0 gran 0 limit 0 flags c0000100 index 64 + PNP: 00ff.2 resource base 1604 size 0 align 0 gran 0 limit 0 flags c0000100 index 66 + PNP: 164e.2 + PNP: 164e.2 resource base 2f8 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60 + PNP: 164e.2 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 + PNP: 164e.2 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74 + PNP: 164e.2 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 75 + PNP: 164e.3 + PNP: 164e.3 resource base 3f8 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60 + PNP: 164e.3 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 + PNP: 164e.7 + PNP: 164e.7 resource base 1680 size 10 align 4 gran 4 limit ffff flags c0000100 index 60 + PNP: 164e.7 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 + PNP: 164e.19 + PNP: 164e.19 resource base 164c size 2 align 1 gran 1 limit ffff flags c0000100 index 60 + PNP: 164e.19 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 + PNP: 002e.0 + PNP: 002e.0 resource base 0 size 8 align 3 gran 3 limit 7ff flags 100 index 60 + PNP: 002e.0 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 + PNP: 002e.0 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74 + PNP: 002e.1 + PNP: 002e.1 resource base 3bc size 400 align 10 gran 10 limit 7ff flags c0000100 index 60 + PNP: 002e.1 resource base 7 size 1 align 0 gran 0 limit 0 flags c0000400 index 70 + PNP: 002e.1 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74 + PNP: 002e.2 + PNP: 002e.2 resource base 2f8 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60 + PNP: 002e.2 resource base 4 size 1 align 0 gran 0 limit 0 flags c0000400 index 70 + PNP: 002e.2 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74 + PNP: 002e.2 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 75 + PNP: 002e.3 + PNP: 002e.3 resource base 3f8 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60 + PNP: 002e.3 resource base 4 size 1 align 0 gran 0 limit 0 flags c0000400 index 70 + PNP: 002e.7 + PNP: 002e.7 resource base 1620 size 8 align 3 gran 3 limit ffff flags c0000100 index 60 + PNP: 002e.7 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 + PNP: 002e.a + PNP: 002e.a resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 60 + PNP: 002e.a resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 + PCI: 00:1f.1 + PCI: 00:1f.1 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 10 + PCI: 00:1f.1 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 14 + PCI: 00:1f.1 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 18 + PCI: 00:1f.1 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 1c + PCI: 00:1f.1 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 index 20 + PCI: 00:1f.2 + PCI: 00:1f.2 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 10 + PCI: 00:1f.2 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 14 + PCI: 00:1f.2 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 18 + PCI: 00:1f.2 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 1c + PCI: 00:1f.2 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 index 20 + PCI: 00:1f.2 resource base 0 size 400 align 10 gran 10 limit ffffffff flags 200 index 24 + PCI: 00:1f.3 child on link 0 I2C: 01:69 + PCI: 00:1f.3 resource base 400 size 20 align 0 gran 0 limit 41f flags f0000100 index 20 + I2C: 01:69 + I2C: 01:54 + I2C: 01:55 + I2C: 01:56 + I2C: 01:57 + I2C: 01:5c + I2C: 01:5d + I2C: 01:5e + I2C: 01:5f +DOMAIN: 0000 compute_resources_io: base: 0 size: 0 align: 0 gran: 0 limit: ffff +PCI: 00:1c.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff +PCI: 01:00.0 18 * [0x0 - 0x1f] io +PCI: 00:1c.0 compute_resources_io: base: 20 size: 1000 align: 12 gran: 12 limit: ffff done +PCI: 00:1c.1 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff +PCI: 00:1c.1 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done +PCI: 00:1c.2 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff +PCI: 00:1c.2 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done +PCI: 00:1c.3 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff +PCI: 00:1c.3 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done +PCI: 00:1e.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff +PCI: 05:00.0 2c * [0x0 - 0xfff] io +PCI: 05:00.0 34 * [0x1000 - 0x1fff] io +PCI: 00:1e.0 compute_resources_io: base: 2000 size: 2000 align: 12 gran: 12 limit: ffff done +PCI: 00:1e.0 1c * [0x0 - 0x1fff] io +PCI: 00:1c.0 1c * [0x2000 - 0x2fff] io +PCI: 00:1d.0 20 * [0x3000 - 0x301f] io +PCI: 00:1d.1 20 * [0x3020 - 0x303f] io +PCI: 00:1d.2 20 * [0x3040 - 0x305f] io +PCI: 00:1d.3 20 * [0x3060 - 0x307f] io +PCI: 00:1f.1 20 * [0x3080 - 0x308f] io +PCI: 00:1f.2 20 * [0x3090 - 0x309f] io +PCI: 00:02.0 14 * [0x30a0 - 0x30a7] io +PCI: 00:1f.1 10 * [0x30a8 - 0x30af] io +PCI: 00:1f.1 18 * [0x30b0 - 0x30b7] io +PCI: 00:1f.2 10 * [0x30b8 - 0x30bf] io +PCI: 00:1f.2 18 * [0x30c0 - 0x30c7] io +PCI: 00:1f.1 14 * [0x30c8 - 0x30cb] io +PCI: 00:1f.1 1c * [0x30cc - 0x30cf] io +PCI: 00:1f.2 14 * [0x30d0 - 0x30d3] io +PCI: 00:1f.2 1c * [0x30d4 - 0x30d7] io +DOMAIN: 0000 compute_resources_io: base: 30d8 size: 30d8 align: 12 gran: 0 limit: ffff done +DOMAIN: 0000 compute_resources_mem: base: 0 size: 0 align: 0 gran: 0 limit: ffffffff +PCI: 00:1c.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff +PCI: 00:1c.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done +PCI: 00:1c.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff +PCI: 01:00.0 10 * [0x0 - 0x1ffff] mem +PCI: 00:1c.0 compute_resources_mem: base: 20000 size: 100000 align: 20 gran: 20 limit: ffffffff done +PCI: 00:1c.1 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff +PCI: 00:1c.1 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done +PCI: 00:1c.1 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff +PCI: 02:00.0 10 * [0x0 - 0xffff] mem +PCI: 00:1c.1 compute_resources_mem: base: 10000 size: 100000 align: 20 gran: 20 limit: ffffffff done +PCI: 00:1c.2 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff +PCI: 00:1c.2 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done +PCI: 00:1c.2 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff +PCI: 00:1c.2 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done +PCI: 00:1c.3 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff +PCI: 00:1c.3 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done +PCI: 00:1c.3 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff +PCI: 00:1c.3 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done +PCI: 00:1e.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff +PCI: 05:00.0 1c * [0x0 - 0x1ffffff] prefmem +PCI: 00:1e.0 compute_resources_prefmem: base: 2000000 size: 2000000 align: 20 gran: 20 limit: ffffffff done +PCI: 00:1e.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff +PCI: 05:00.0 24 * [0x0 - 0x1ffffff] mem +PCI: 05:00.0 10 * [0x2000000 - 0x2000fff] mem +PCI: 05:00.1 10 * [0x2001000 - 0x20017ff] mem +PCI: 05:00.2 10 * [0x2001800 - 0x20018ff] mem +PCI: 05:00.3 10 * [0x2001900 - 0x20019ff] mem +PCI: 00:1e.0 compute_resources_mem: base: 2001a00 size: 2100000 align: 20 gran: 20 limit: ffffffff done +PCI: 00:02.0 18 * [0x0 - 0xfffffff] prefmem +PCI: 00:1e.0 20 * [0x10000000 - 0x120fffff] mem +PCI: 00:1e.0 24 * [0x12100000 - 0x140fffff] prefmem +PCI: 00:1c.0 20 * [0x14100000 - 0x141fffff] mem +PCI: 00:1c.1 20 * [0x14200000 - 0x142fffff] mem +PCI: 00:02.0 10 * [0x14300000 - 0x1437ffff] mem +PCI: 00:02.1 10 * [0x14380000 - 0x143fffff] mem +PCI: 00:02.0 1c * [0x14400000 - 0x1443ffff] mem +PCI: 00:1b.0 10 * [0x14440000 - 0x14443fff] mem +PCI: 00:1d.7 10 * [0x14444000 - 0x144443ff] mem +PCI: 00:1f.2 24 * [0x14444400 - 0x144447ff] mem +DOMAIN: 0000 compute_resources_mem: base: 14444800 size: 14444800 align: 28 gran: 0 limit: ffffffff done +avoid_fixed_resources: DOMAIN: 0000 +avoid_fixed_resources:@DOMAIN: 0000 10000000 limit 0000ffff +avoid_fixed_resources:@DOMAIN: 0000 10000100 limit ffffffff +constrain_resources: DOMAIN: 0000 +constrain_resources: PCI: 00:00.0 +constrain_resources: PCI: 00:02.0 +constrain_resources: PCI: 00:02.1 +constrain_resources: PCI: 00:1b.0 +constrain_resources: PCI: 00:1c.0 +constrain_resources: PCI: 01:00.0 +constrain_resources: PCI: 00:1c.1 +constrain_resources: PCI: 02:00.0 +constrain_resources: PCI: 00:1c.2 +constrain_resources: PCI: 00:1c.3 +constrain_resources: PCI: 00:1d.0 +constrain_resources: PCI: 00:1d.1 +constrain_resources: PCI: 00:1d.2 +constrain_resources: PCI: 00:1d.3 +constrain_resources: PCI: 00:1d.7 +constrain_resources: PCI: 00:1e.0 +constrain_resources: PCI: 05:00.0 +constrain_resources: PCI: 05:00.1 +constrain_resources: PCI: 05:00.2 +constrain_resources: PCI: 05:00.3 +constrain_resources: PCI: 00:1f.0 +constrain_resources: PNP: 00ff.1 +constrain_resources: PNP: 00ff.2 +skipping PNP: 00ff.2@60 fixed resource, size=0! +skipping PNP: 00ff.2@62 fixed resource, size=0! +skipping PNP: 00ff.2@64 fixed resource, size=0! +skipping PNP: 00ff.2@66 fixed resource, size=0! +constrain_resources: PNP: 164e.2 +constrain_resources: PNP: 164e.7 +constrain_resources: PNP: 164e.19 +constrain_resources: PNP: 002e.1 +constrain_resources: PNP: 002e.3 +constrain_resources: PNP: 002e.7 +constrain_resources: PCI: 00:1f.1 +constrain_resources: PCI: 00:1f.2 +constrain_resources: PCI: 00:1f.3 +constrain_resources: I2C: 01:69 +constrain_resources: I2C: 01:54 +constrain_resources: I2C: 01:55 +constrain_resources: I2C: 01:56 +constrain_resources: I2C: 01:57 +constrain_resources: I2C: 01:5c +constrain_resources: I2C: 01:5d +constrain_resources: I2C: 01:5e +constrain_resources: I2C: 01:5f +avoid_fixed_resources2: DOMAIN: 0000@10000000 limit 0000ffff + lim->base 00001690 lim->limit 0000ffff +avoid_fixed_resources2: DOMAIN: 0000@10000100 limit ffffffff + lim->base 00000000 lim->limit efffffff +Setting resources... +DOMAIN: 0000 allocate_resources_io: base:1690 size:30d8 align:12 gran:0 limit:ffff +Assigned: PCI: 00:1e.0 1c * [0x2000 - 0x3fff] io +Assigned: PCI: 00:1c.0 1c * [0x4000 - 0x4fff] io +Assigned: PCI: 00:1d.0 20 * [0x5000 - 0x501f] io +Assigned: PCI: 00:1d.1 20 * [0x5020 - 0x503f] io +Assigned: PCI: 00:1d.2 20 * [0x5040 - 0x505f] io +Assigned: PCI: 00:1d.3 20 * [0x5060 - 0x507f] io +Assigned: PCI: 00:1f.1 20 * [0x5080 - 0x508f] io +Assigned: PCI: 00:1f.2 20 * [0x5090 - 0x509f] io +Assigned: PCI: 00:02.0 14 * [0x50a0 - 0x50a7] io +Assigned: PCI: 00:1f.1 10 * [0x50a8 - 0x50af] io +Assigned: PCI: 00:1f.1 18 * [0x50b0 - 0x50b7] io +Assigned: PCI: 00:1f.2 10 * [0x50b8 - 0x50bf] io +Assigned: PCI: 00:1f.2 18 * [0x50c0 - 0x50c7] io +Assigned: PCI: 00:1f.1 14 * [0x50c8 - 0x50cb] io +Assigned: PCI: 00:1f.1 1c * [0x50cc - 0x50cf] io +Assigned: PCI: 00:1f.2 14 * [0x50d0 - 0x50d3] io +Assigned: PCI: 00:1f.2 1c * [0x50d4 - 0x50d7] io +DOMAIN: 0000 allocate_resources_io: next_base: 50d8 size: 30d8 align: 12 gran: 0 done +PCI: 00:1c.0 allocate_resources_io: base:4000 size:1000 align:12 gran:12 limit:ffff +Assigned: PCI: 01:00.0 18 * [0x4000 - 0x401f] io +PCI: 00:1c.0 allocate_resources_io: next_base: 4020 size: 1000 align: 12 gran: 12 done +PCI: 00:1c.1 allocate_resources_io: base:ffff size:0 align:12 gran:12 limit:ffff +PCI: 00:1c.1 allocate_resources_io: next_base: ffff size: 0 align: 12 gran: 12 done +PCI: 00:1c.2 allocate_resources_io: base:ffff size:0 align:12 gran:12 limit:ffff +PCI: 00:1c.2 allocate_resources_io: next_base: ffff size: 0 align: 12 gran: 12 done +PCI: 00:1c.3 allocate_resources_io: base:ffff size:0 align:12 gran:12 limit:ffff +PCI: 00:1c.3 allocate_resources_io: next_base: ffff size: 0 align: 12 gran: 12 done +PCI: 00:1e.0 allocate_resources_io: base:2000 size:2000 align:12 gran:12 limit:ffff +Assigned: PCI: 05:00.0 2c * [0x2000 - 0x2fff] io +Assigned: PCI: 05:00.0 34 * [0x3000 - 0x3fff] io +PCI: 00:1e.0 allocate_resources_io: next_base: 4000 size: 2000 align: 12 gran: 12 done +DOMAIN: 0000 allocate_resources_mem: base:d0000000 size:14444800 align:28 gran:0 limit:efffffff +Assigned: PCI: 00:02.0 18 * [0xd0000000 - 0xdfffffff] prefmem +Assigned: PCI: 00:1e.0 20 * [0xe0000000 - 0xe20fffff] mem +Assigned: PCI: 00:1e.0 24 * [0xe2100000 - 0xe40fffff] prefmem +Assigned: PCI: 00:1c.0 20 * [0xe4100000 - 0xe41fffff] mem +Assigned: PCI: 00:1c.1 20 * [0xe4200000 - 0xe42fffff] mem +Assigned: PCI: 00:02.0 10 * [0xe4300000 - 0xe437ffff] mem +Assigned: PCI: 00:02.1 10 * [0xe4380000 - 0xe43fffff] mem +Assigned: PCI: 00:02.0 1c * [0xe4400000 - 0xe443ffff] mem +Assigned: PCI: 00:1b.0 10 * [0xe4440000 - 0xe4443fff] mem +Assigned: PCI: 00:1d.7 10 * [0xe4444000 - 0xe44443ff] mem +Assigned: PCI: 00:1f.2 24 * [0xe4444400 - 0xe44447ff] mem +DOMAIN: 0000 allocate_resources_mem: next_base: e4444800 size: 14444800 align: 28 gran: 0 done +PCI: 00:1c.0 allocate_resources_prefmem: base:efffffff size:0 align:20 gran:20 limit:efffffff +PCI: 00:1c.0 allocate_resources_prefmem: next_base: efffffff size: 0 align: 20 gran: 20 done +PCI: 00:1c.0 allocate_resources_mem: base:e4100000 size:100000 align:20 gran:20 limit:efffffff +Assigned: PCI: 01:00.0 10 * [0xe4100000 - 0xe411ffff] mem +PCI: 00:1c.0 allocate_resources_mem: next_base: e4120000 size: 100000 align: 20 gran: 20 done +PCI: 00:1c.1 allocate_resources_prefmem: base:efffffff size:0 align:20 gran:20 limit:efffffff +PCI: 00:1c.1 allocate_resources_prefmem: next_base: efffffff size: 0 align: 20 gran: 20 done +PCI: 00:1c.1 allocate_resources_mem: base:e4200000 size:100000 align:20 gran:20 limit:efffffff +Assigned: PCI: 02:00.0 10 * [0xe4200000 - 0xe420ffff] mem +PCI: 00:1c.1 allocate_resources_mem: next_base: e4210000 size: 100000 align: 20 gran: 20 done +PCI: 00:1c.2 allocate_resources_prefmem: base:efffffff size:0 align:20 gran:20 limit:efffffff +PCI: 00:1c.2 allocate_resources_prefmem: next_base: efffffff size: 0 align: 20 gran: 20 done +PCI: 00:1c.2 allocate_resources_mem: base:efffffff size:0 align:20 gran:20 limit:efffffff +PCI: 00:1c.2 allocate_resources_mem: next_base: efffffff size: 0 align: 20 gran: 20 done +PCI: 00:1c.3 allocate_resources_prefmem: base:efffffff size:0 align:20 gran:20 limit:efffffff +PCI: 00:1c.3 allocate_resources_prefmem: next_base: efffffff size: 0 align: 20 gran: 20 done +PCI: 00:1c.3 allocate_resources_mem: base:efffffff size:0 align:20 gran:20 limit:efffffff +PCI: 00:1c.3 allocate_resources_mem: next_base: efffffff size: 0 align: 20 gran: 20 done +PCI: 00:1e.0 allocate_resources_prefmem: base:e2100000 size:2000000 align:20 gran:20 limit:efffffff +Assigned: PCI: 05:00.0 1c * [0xe2100000 - 0xe40fffff] prefmem +PCI: 00:1e.0 allocate_resources_prefmem: next_base: e4100000 size: 2000000 align: 20 gran: 20 done +PCI: 00:1e.0 allocate_resources_mem: base:e0000000 size:2100000 align:20 gran:20 limit:efffffff +Assigned: PCI: 05:00.0 24 * [0xe0000000 - 0xe1ffffff] mem +Assigned: PCI: 05:00.0 10 * [0xe2000000 - 0xe2000fff] mem +Assigned: PCI: 05:00.1 10 * [0xe2001000 - 0xe20017ff] mem +Assigned: PCI: 05:00.2 10 * [0xe2001800 - 0xe20018ff] mem +Assigned: PCI: 05:00.3 10 * [0xe2001900 - 0xe20019ff] mem +PCI: 00:1e.0 allocate_resources_mem: next_base: e2001a00 size: 2100000 align: 20 gran: 20 done +Root Device assign_resources, bus 0 link: 0 +pci_tolm: 0xd0000000 +Base of stolen memory: 0xbf800000 +Top of Low Used DRAM: 0xc0000000 +IGD decoded, subtracting 8M UMA +Available memory: 3137536K (3064M) +Adding PCIe config bar +DOMAIN: 0000 assign_resources, bus 0 link: 0 +PCI: 00:00.0 cf <- [0x00f0000000 - 0x00f3ffffff] size 0x04000000 gran 0x00 mem<mmconfig> +PCI: 00:02.0 10 <- [0x00e4300000 - 0x00e437ffff] size 0x00080000 gran 0x13 mem +PCI: 00:02.0 14 <- [0x00000050a0 - 0x00000050a7] size 0x00000008 gran 0x03 io +PCI: 00:02.0 18 <- [0x00d0000000 - 0x00dfffffff] size 0x10000000 gran 0x1c prefmem +PCI: 00:02.0 1c <- [0x00e4400000 - 0x00e443ffff] size 0x00040000 gran 0x12 mem +PCI: 00:02.1 10 <- [0x00e4380000 - 0x00e43fffff] size 0x00080000 gran 0x13 mem +PCI: 00:1b.0 10 <- [0x00e4440000 - 0x00e4443fff] size 0x00004000 gran 0x0e mem64 +PCI: 00:1c.0 1c <- [0x0000004000 - 0x0000004fff] size 0x00001000 gran 0x0c bus 01 io +PCI: 00:1c.0 24 <- [0x00efffffff - 0x00effffffe] size 0x00000000 gran 0x14 bus 01 prefmem +PCI: 00:1c.0 20 <- [0x00e4100000 - 0x00e41fffff] size 0x00100000 gran 0x14 bus 01 mem +PCI: 00:1c.0 assign_resources, bus 1 link: 0 +PCI: 01:00.0 10 <- [0x00e4100000 - 0x00e411ffff] size 0x00020000 gran 0x11 mem +PCI: 01:00.0 18 <- [0x0000004000 - 0x000000401f] size 0x00000020 gran 0x05 io +PCI: 00:1c.0 assign_resources, bus 1 link: 0 +PCI: 00:1c.1 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 02 io +PCI: 00:1c.1 24 <- [0x00efffffff - 0x00effffffe] size 0x00000000 gran 0x14 bus 02 prefmem +PCI: 00:1c.1 20 <- [0x00e4200000 - 0x00e42fffff] size 0x00100000 gran 0x14 bus 02 mem +PCI: 00:1c.1 assign_resources, bus 2 link: 0 +PCI: 02:00.0 10 <- [0x00e4200000 - 0x00e420ffff] size 0x00010000 gran 0x10 mem64 +PCI: 00:1c.1 assign_resources, bus 2 link: 0 +PCI: 00:1c.2 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 03 io +PCI: 00:1c.2 24 <- [0x00efffffff - 0x00effffffe] size 0x00000000 gran 0x14 bus 03 prefmem +PCI: 00:1c.2 20 <- [0x00efffffff - 0x00effffffe] size 0x00000000 gran 0x14 bus 03 mem +PCI: 00:1c.3 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 04 io +PCI: 00:1c.3 24 <- [0x00efffffff - 0x00effffffe] size 0x00000000 gran 0x14 bus 04 prefmem +PCI: 00:1c.3 20 <- [0x00efffffff - 0x00effffffe] size 0x00000000 gran 0x14 bus 04 mem +PCI: 00:1d.0 20 <- [0x0000005000 - 0x000000501f] size 0x00000020 gran 0x05 io +PCI: 00:1d.1 20 <- [0x0000005020 - 0x000000503f] size 0x00000020 gran 0x05 io +PCI: 00:1d.2 20 <- [0x0000005040 - 0x000000505f] size 0x00000020 gran 0x05 io +PCI: 00:1d.3 20 <- [0x0000005060 - 0x000000507f] size 0x00000020 gran 0x05 io +PCI: 00:1d.7 10 <- [0x00e4444000 - 0x00e44443ff] size 0x00000400 gran 0x0a mem +PCI: 00:1e.0 1c <- [0x0000002000 - 0x0000003fff] size 0x00002000 gran 0x0c bus 05 io +PCI: 00:1e.0 24 <- [0x00e2100000 - 0x00e40fffff] size 0x02000000 gran 0x14 bus 05 prefmem +PCI: 00:1e.0 20 <- [0x00e0000000 - 0x00e20fffff] size 0x02100000 gran 0x14 bus 05 mem +PCI: 00:1e.0 assign_resources, bus 5 link: 0 +PCI: 05:00.0 In set resources +PCI: 05:00.0 10 <- [0x00e2000000 - 0x00e2000fff] size 0x00001000 gran 0x0c mem +PCI: 05:00.0 2c <- [0x0000002000 - 0x0000002fff] size 0x00001000 gran 0x02 io +PCI: 05:00.0 34 <- [0x0000003000 - 0x0000003fff] size 0x00001000 gran 0x02 io +PCI: 05:00.0 1c <- [0x00e2100000 - 0x00e40fffff] size 0x02000000 gran 0x0c prefmem +PCI: 05:00.0 24 <- [0x00e0000000 - 0x00e1ffffff] size 0x02000000 gran 0x0c mem +PCI: 05:00.1 10 <- [0x00e2001000 - 0x00e20017ff] size 0x00000800 gran 0x0b mem +PCI: 05:00.2 10 <- [0x00e2001800 - 0x00e20018ff] size 0x00000100 gran 0x08 mem +PCI: 05:00.3 10 <- [0x00e2001900 - 0x00e20019ff] size 0x00000100 gran 0x08 mem +PCI: 00:1e.0 assign_resources, bus 5 link: 0 +PCI: 00:1f.0 assign_resources, bus 0 link: 0 +PNP: 00ff.1 missing set_resources +PNP: 00ff.2 missing set_resources +PNP: 164e.2 60 <- [0x00000002f8 - 0x00000002ff] size 0x00000008 gran 0x03 io +ERROR: PNP: 164e.2 70 irq size: 0x0000000001 not assigned +ERROR: PNP: 164e.2 74 drq size: 0x0000000001 not assigned +ERROR: PNP: 164e.2 75 drq size: 0x0000000001 not assigned +PNP: 164e.7 60 <- [0x0000001680 - 0x000000168f] size 0x00000010 gran 0x04 io +ERROR: PNP: 164e.7 70 irq size: 0x0000000001 not assigned +PNP: 164e.19 60 <- [0x000000164c - 0x000000164d] size 0x00000002 gran 0x01 io +ERROR: PNP: 164e.19 70 irq size: 0x0000000001 not assigned +PNP: 002e.1 60 <- [0x00000003bc - 0x00000007bb] size 0x00000400 gran 0x0a io +PNP: 002e.1 70 <- [0x0000000007 - 0x0000000007] size 0x00000001 gran 0x00 irq +ERROR: PNP: 002e.1 74 drq size: 0x0000000001 not assigned +PNP: 002e.3 60 <- [0x00000003f8 - 0x00000003ff] size 0x00000008 gran 0x03 io +PNP: 002e.3 70 <- [0x0000000004 - 0x0000000004] size 0x00000001 gran 0x00 irq +PNP: 002e.7 60 <- [0x0000001620 - 0x0000001627] size 0x00000008 gran 0x03 io +ERROR: PNP: 002e.7 70 irq size: 0x0000000001 not assigned +PCI: 00:1f.0 assign_resources, bus 0 link: 0 +PCI: 00:1f.1 10 <- [0x00000050a8 - 0x00000050af] size 0x00000008 gran 0x03 io +PCI: 00:1f.1 14 <- [0x00000050c8 - 0x00000050cb] size 0x00000004 gran 0x02 io +PCI: 00:1f.1 18 <- [0x00000050b0 - 0x00000050b7] size 0x00000008 gran 0x03 io +PCI: 00:1f.1 1c <- [0x00000050cc - 0x00000050cf] size 0x00000004 gran 0x02 io +PCI: 00:1f.1 20 <- [0x0000005080 - 0x000000508f] size 0x00000010 gran 0x04 io +PCI: 00:1f.2 10 <- [0x00000050b8 - 0x00000050bf] size 0x00000008 gran 0x03 io +PCI: 00:1f.2 14 <- [0x00000050d0 - 0x00000050d3] size 0x00000004 gran 0x02 io +PCI: 00:1f.2 18 <- [0x00000050c0 - 0x00000050c7] size 0x00000008 gran 0x03 io +PCI: 00:1f.2 1c <- [0x00000050d4 - 0x00000050d7] size 0x00000004 gran 0x02 io +PCI: 00:1f.2 20 <- [0x0000005090 - 0x000000509f] size 0x00000010 gran 0x04 io +PCI: 00:1f.2 24 <- [0x00e4444400 - 0x00e44447ff] size 0x00000400 gran 0x0a mem +PCI: 00:1f.3 assign_resources, bus 1 link: 0 +PCI: 00:1f.3 assign_resources, bus 1 link: 0 +DOMAIN: 0000 assign_resources, bus 0 link: 0 +CBMEM region bf6d0000-bf7fffff (cbmem_late_set_table) +Root Device assign_resources, bus 0 link: 0 +Done setting resources. +Show resources in subtree (Root Device)...After assigning values. + Root Device child on link 0 CPU_CLUSTER: 0 + CPU_CLUSTER: 0 child on link 0 APIC: 00 + APIC: 00 + DOMAIN: 0000 child on link 0 PCI: 00:00.0 + DOMAIN: 0000 resource base 1690 size 30d8 align 12 gran 0 limit ffff flags 40040100 index 10000000 + DOMAIN: 0000 resource base d0000000 size 14444800 align 28 gran 0 limit efffffff flags 40040200 index 10000100 + DOMAIN: 0000 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 3 + DOMAIN: 0000 resource base c0000 size bff40000 align 0 gran 0 limit 0 flags e0004200 index 4 + DOMAIN: 0000 resource base bf800000 size 800000 align 0 gran 0 limit 0 flags f0000200 index 5 + DOMAIN: 0000 resource base f0000000 size 4000000 align 0 gran 0 limit 0 flags f0000200 index 7 + PCI: 00:00.0 + PCI: 00:00.0 resource base f0000000 size 4000000 align 0 gran 0 limit 0 flags e0000200 index cf + PCI: 00:02.0 + PCI: 00:02.0 resource base e4300000 size 80000 align 19 gran 19 limit efffffff flags 60000200 index 10 + PCI: 00:02.0 resource base 50a0 size 8 align 3 gran 3 limit ffff flags 60000100 index 14 + PCI: 00:02.0 resource base d0000000 size 10000000 align 28 gran 28 limit efffffff flags 60001200 index 18 + PCI: 00:02.0 resource base e4400000 size 40000 align 18 gran 18 limit efffffff flags 60000200 index 1c + PCI: 00:02.1 + PCI: 00:02.1 resource base e4380000 size 80000 align 19 gran 19 limit efffffff flags 60000200 index 10 + PCI: 00:1b.0 + PCI: 00:1b.0 resource base e4440000 size 4000 align 14 gran 14 limit efffffff flags 60000201 index 10 + PCI: 00:1c.0 child on link 0 PCI: 01:00.0 + PCI: 00:1c.0 resource base 4000 size 1000 align 12 gran 12 limit ffff flags 60080102 index 1c + PCI: 00:1c.0 resource base efffffff size 0 align 20 gran 20 limit efffffff flags 60081202 index 24 + PCI: 00:1c.0 resource base e4100000 size 100000 align 20 gran 20 limit efffffff flags 60080202 index 20 + PCI: 01:00.0 + PCI: 01:00.0 resource base e4100000 size 20000 align 17 gran 17 limit efffffff flags 60000200 index 10 + PCI: 01:00.0 resource base 4000 size 20 align 5 gran 5 limit ffff flags 60000100 index 18 + PCI: 00:1c.1 child on link 0 PCI: 02:00.0 + PCI: 00:1c.1 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c + PCI: 00:1c.1 resource base efffffff size 0 align 20 gran 20 limit efffffff flags 60081202 index 24 + PCI: 00:1c.1 resource base e4200000 size 100000 align 20 gran 20 limit efffffff flags 60080202 index 20 + PCI: 02:00.0 + PCI: 02:00.0 resource base e4200000 size 10000 align 16 gran 16 limit efffffff flags 60000201 index 10 + PCI: 00:1c.2 + PCI: 00:1c.2 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c + PCI: 00:1c.2 resource base efffffff size 0 align 20 gran 20 limit efffffff flags 60081202 index 24 + PCI: 00:1c.2 resource base efffffff size 0 align 20 gran 20 limit efffffff flags 60080202 index 20 + PCI: 00:1c.3 + PCI: 00:1c.3 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c + PCI: 00:1c.3 resource base efffffff size 0 align 20 gran 20 limit efffffff flags 60081202 index 24 + PCI: 00:1c.3 resource base efffffff size 0 align 20 gran 20 limit efffffff flags 60080202 index 20 + PCI: 00:1d.0 + PCI: 00:1d.0 resource base 5000 size 20 align 5 gran 5 limit ffff flags 60000100 index 20 + PCI: 00:1d.1 + PCI: 00:1d.1 resource base 5020 size 20 align 5 gran 5 limit ffff flags 60000100 index 20 + PCI: 00:1d.2 + PCI: 00:1d.2 resource base 5040 size 20 align 5 gran 5 limit ffff flags 60000100 index 20 + PCI: 00:1d.3 + PCI: 00:1d.3 resource base 5060 size 20 align 5 gran 5 limit ffff flags 60000100 index 20 + PCI: 00:1d.7 + PCI: 00:1d.7 resource base e4444000 size 400 align 10 gran 10 limit efffffff flags 60000200 index 10 + PCI: 00:1e.0 child on link 0 PCI: 05:00.0 + PCI: 00:1e.0 resource base 2000 size 2000 align 12 gran 12 limit ffff flags 60080102 index 1c + PCI: 00:1e.0 resource base e2100000 size 2000000 align 20 gran 20 limit efffffff flags 60081202 index 24 + PCI: 00:1e.0 resource base e0000000 size 2100000 align 20 gran 20 limit efffffff flags 60080202 index 20 + PCI: 05:00.0 + PCI: 05:00.0 resource base e2000000 size 1000 align 12 gran 12 limit efffffff flags 60000200 index 10 + PCI: 05:00.0 resource base 2000 size 1000 align 2 gran 2 limit ffff flags 60000100 index 2c + PCI: 05:00.0 resource base 3000 size 1000 align 2 gran 2 limit ffff flags 60000100 index 34 + PCI: 05:00.0 resource base e2100000 size 2000000 align 12 gran 12 limit efffffff flags 60001200 index 1c + PCI: 05:00.0 resource base e0000000 size 2000000 align 12 gran 12 limit efffffff flags 60000200 index 24 + PCI: 05:00.1 + PCI: 05:00.1 resource base e2001000 size 800 align 11 gran 11 limit efffffff flags 60000200 index 10 + PCI: 05:00.2 + PCI: 05:00.2 resource base e2001800 size 100 align 8 gran 8 limit efffffff flags 60000200 index 10 + PCI: 05:00.3 + PCI: 05:00.3 resource base e2001900 size 100 align 8 gran 8 limit efffffff flags 60000200 index 10 + PCI: 00:1f.0 child on link 0 PNP: 00ff.1 + PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000 + PCI: 00:1f.0 resource base ff800000 size 800000 align 0 gran 0 limit 0 flags c0040200 index 10000100 + PCI: 00:1f.0 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3 + PNP: 00ff.1 + PNP: 00ff.1 resource base 15e0 size 10 align 5 gran 5 limit 0 flags 80000100 index 77 + PNP: 00ff.2 + PNP: 00ff.2 resource base 62 size 0 align 0 gran 0 limit 0 flags c0000100 index 60 + PNP: 00ff.2 resource base 66 size 0 align 0 gran 0 limit 0 flags c0000100 index 62 + PNP: 00ff.2 resource base 1600 size 0 align 0 gran 0 limit 0 flags c0000100 index 64 + PNP: 00ff.2 resource base 1604 size 0 align 0 gran 0 limit 0 flags c0000100 index 66 + PNP: 164e.2 + PNP: 164e.2 resource base 2f8 size 8 align 3 gran 3 limit 7ff flags e0000100 index 60 + PNP: 164e.2 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 + PNP: 164e.2 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74 + PNP: 164e.2 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 75 + PNP: 164e.3 + PNP: 164e.3 resource base 3f8 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60 + PNP: 164e.3 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 + PNP: 164e.7 + PNP: 164e.7 resource base 1680 size 10 align 4 gran 4 limit ffff flags e0000100 index 60 + PNP: 164e.7 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 + PNP: 164e.19 + PNP: 164e.19 resource base 164c size 2 align 1 gran 1 limit ffff flags e0000100 index 60 + PNP: 164e.19 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 + PNP: 002e.0 + PNP: 002e.0 resource base 0 size 8 align 3 gran 3 limit 7ff flags 100 index 60 + PNP: 002e.0 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 + PNP: 002e.0 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74 + PNP: 002e.1 + PNP: 002e.1 resource base 3bc size 400 align 10 gran 10 limit 7ff flags e0000100 index 60 + PNP: 002e.1 resource base 7 size 1 align 0 gran 0 limit 0 flags e0000400 index 70 + PNP: 002e.1 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74 + PNP: 002e.2 + PNP: 002e.2 resource base 2f8 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60 + PNP: 002e.2 resource base 4 size 1 align 0 gran 0 limit 0 flags c0000400 index 70 + PNP: 002e.2 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74 + PNP: 002e.2 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 75 + PNP: 002e.3 + PNP: 002e.3 resource base 3f8 size 8 align 3 gran 3 limit 7ff flags e0000100 index 60 + PNP: 002e.3 resource base 4 size 1 align 0 gran 0 limit 0 flags e0000400 index 70 + PNP: 002e.7 + PNP: 002e.7 resource base 1620 size 8 align 3 gran 3 limit ffff flags e0000100 index 60 + PNP: 002e.7 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 + PNP: 002e.a + PNP: 002e.a resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 60 + PNP: 002e.a resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 + PCI: 00:1f.1 + PCI: 00:1f.1 resource base 50a8 size 8 align 3 gran 3 limit ffff flags 60000100 index 10 + PCI: 00:1f.1 resource base 50c8 size 4 align 2 gran 2 limit ffff flags 60000100 index 14 + PCI: 00:1f.1 resource base 50b0 size 8 align 3 gran 3 limit ffff flags 60000100 index 18 + PCI: 00:1f.1 resource base 50cc size 4 align 2 gran 2 limit ffff flags 60000100 index 1c + PCI: 00:1f.1 resource base 5080 size 10 align 4 gran 4 limit ffff flags 60000100 index 20 + PCI: 00:1f.2 + PCI: 00:1f.2 resource base 50b8 size 8 align 3 gran 3 limit ffff flags 60000100 index 10 + PCI: 00:1f.2 resource base 50d0 size 4 align 2 gran 2 limit ffff flags 60000100 index 14 + PCI: 00:1f.2 resource base 50c0 size 8 align 3 gran 3 limit ffff flags 60000100 index 18 + PCI: 00:1f.2 resource base 50d4 size 4 align 2 gran 2 limit ffff flags 60000100 index 1c + PCI: 00:1f.2 resource base 5090 size 10 align 4 gran 4 limit ffff flags 60000100 index 20 + PCI: 00:1f.2 resource base e4444400 size 400 align 10 gran 10 limit efffffff flags 60000200 index 24 + PCI: 00:1f.3 child on link 0 I2C: 01:69 + PCI: 00:1f.3 resource base 400 size 20 align 0 gran 0 limit 41f flags f0000100 index 20 + I2C: 01:69 + I2C: 01:54 + I2C: 01:55 + I2C: 01:56 + I2C: 01:57 + I2C: 01:5c + I2C: 01:5d + I2C: 01:5e + I2C: 01:5f +Done allocating resources. +BS: Exiting BS_DEV_RESOURCES state. +BS: BS_DEV_RESOURCES times (us): entry 0 run 3353777 exit 0 +BS: Entering BS_DEV_ENABLE state. +Enabling resources... +PCI: 00:00.0 subsystem <- 17aa/2017 +PCI: 00:00.0 cmd <- 06 +PCI: 00:02.0 subsystem <- 17aa/201a +PCI: 00:02.0 cmd <- 03 +PCI: 00:02.1 subsystem <- 17aa/201a +PCI: 00:02.1 cmd <- 02 +PCI: 00:1b.0 subsystem <- 17aa/2010 +PCI: 00:1b.0 cmd <- 102 +PCI: 00:1c.0 bridge ctrl <- 0003 +PCI: 00:1c.0 subsystem <- 0000/0000 +PCI: 00:1c.0 cmd <- 107 +PCI: 00:1c.1 bridge ctrl <- 0003 +PCI: 00:1c.1 subsystem <- 0000/0000 +PCI: 00:1c.1 cmd <- 106 +PCI: 00:1c.2 bridge ctrl <- 0003 +PCI: 00:1c.2 cmd <- 00 +PCI: 00:1c.3 bridge ctrl <- 0003 +PCI: 00:1c.3 cmd <- 00 +PCI: 00:1d.0 subsystem <- 17aa/200a +PCI: 00:1d.0 cmd <- 01 +PCI: 00:1d.1 subsystem <- 17aa/200a +PCI: 00:1d.1 cmd <- 01 +PCI: 00:1d.2 subsystem <- 17aa/200a +PCI: 00:1d.2 cmd <- 01 +PCI: 00:1d.3 subsystem <- 17aa/200a +PCI: 00:1d.3 cmd <- 01 +PCI: 00:1d.7 subsystem <- 17aa/200b +PCI: 00:1d.7 cmd <- 102 +PCI: 00:1e.0 bridge ctrl <- 0003 +PCI: 00:1e.0 cmd <- 07 (NOT WRITTEN!) +PCI: 00:1f.0 subsystem <- 17aa/2009 +PCI: 00:1f.0 cmd <- 107 +PCI: 00:1f.1 subsystem <- 17aa/200c +PCI: 00:1f.1 cmd <- 01 +PCI: 00:1f.2 subsystem <- 17aa/200d +PCI: 00:1f.2 cmd <- 03 +PCI: 00:1f.3 subsystem <- 17aa/200f +PCI: 00:1f.3 cmd <- 101 +PCI: 01:00.0 cmd <- 03 +PCI: 02:00.0 cmd <- 02 +PCI: 05:00.0 bridge ctrl <- 0503 +PCI: 05:00.0 cmd <- 03 +PCI: 05:00.1 cmd <- 02 +PCI: 05:00.2 cmd <- 06 +PCI: 05:00.3 cmd <- 06 +done. +BS: Exiting BS_DEV_ENABLE state. +BS: BS_DEV_ENABLE times (us): entry 0 run 124466 exit 0 +BS: Entering BS_DEV_INIT state. +Initializing devices... +Root Device init +recv_ec_data: 0x11 +recv_ec_data: 0x11 +Root Device init 5771 usecs +CPU_CLUSTER: 0 init +start_eip=0x00001000, code_size=0x00000031 +Initializing SMM handler... ... pmbase = 0x0500 + +SMI_STS: MCSMI PM1 +PM1_STS: WAK PWRBTN TMROF +GPE0_STS: GPIO15 GPIO14 GPIO13 GPIO12 GPIO11 GPIO10 GPIO8 GPIO7 GPIO6 GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0 +ALT_GP_SMI_STS: GPI15 GPI14 GPI13 GPI12 GPI11 GPI10 GPI8 GPI7 GPI6 GPI5 GPI4 GPI3 GPI2 GPI1 GPI0 +TCO_STS: INTRD_DET + ... raise SMI# +Initializing CPU #0 +CPU: vendor Intel device 6ec +CPU: family 06, model 0e, stepping 0c +Enabling cache +microcode: sig=0x6ec pf=0x20 revision=0x0 +Microcode size field is 0 +Microcode size field is 0 +Microcode size field is 0 +Microcode size field is 0 +microcode: updated to revision 0x54 date=2006-05-01 +CPU: Intel(R) Core(TM) Duo CPU L2400 @ 1.66GHz. +MTRR: Physical address space: +0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6 +0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0 +0x00000000000c0000 - 0x00000000bf800000 size 0xbf740000 type 6 +0x00000000bf800000 - 0x00000000d0000000 size 0x10800000 type 0 +0x00000000d0000000 - 0x00000000e0000000 size 0x10000000 type 1 +0x00000000e0000000 - 0x0000000100000000 size 0x20000000 type 0 +MTRR addr 0x0-0x10 set to 6 type @ 0 +MTRR addr 0x10-0x20 set to 6 type @ 1 +MTRR addr 0x20-0x30 set to 6 type @ 2 +MTRR addr 0x30-0x40 set to 6 type @ 3 +MTRR addr 0x40-0x50 set to 6 type @ 4 +MTRR addr 0x50-0x60 set to 6 type @ 5 +MTRR addr 0x60-0x70 set to 6 type @ 6 +MTRR addr 0x70-0x80 set to 6 type @ 7 +MTRR addr 0x80-0x84 set to 6 type @ 8 +MTRR addr 0x84-0x88 set to 6 type @ 9 +MTRR addr 0x88-0x8c set to 6 type @ 10 +MTRR addr 0x8c-0x90 set to 6 type @ 11 +MTRR addr 0x90-0x94 set to 6 type @ 12 +MTRR addr 0x94-0x98 set to 6 type @ 13 +MTRR addr 0x98-0x9c set to 6 type @ 14 +MTRR addr 0x9c-0xa0 set to 6 type @ 15 +MTRR addr 0xa0-0xa4 set to 0 type @ 16 +MTRR addr 0xa4-0xa8 set to 0 type @ 17 +MTRR addr 0xa8-0xac set to 0 type @ 18 +MTRR addr 0xac-0xb0 set to 0 type @ 19 +MTRR addr 0xb0-0xb4 set to 0 type @ 20 +MTRR addr 0xb4-0xb8 set to 0 type @ 21 +MTRR addr 0xb8-0xbc set to 0 type @ 22 +MTRR addr 0xbc-0xc0 set to 0 type @ 23 +MTRR addr 0xc0-0xc1 set to 6 type @ 24 +MTRR addr 0xc1-0xc2 set to 6 type @ 25 +MTRR addr 0xc2-0xc3 set to 6 type @ 26 +MTRR addr 0xc3-0xc4 set to 6 type @ 27 +MTRR addr 0xc4-0xc5 set to 6 type @ 28 +MTRR addr 0xc5-0xc6 set to 6 type @ 29 +MTRR addr 0xc6-0xc7 set to 6 type @ 30 +MTRR addr 0xc7-0xc8 set to 6 type @ 31 +MTRR addr 0xc8-0xc9 set to 6 type @ 32 +MTRR addr 0xc9-0xca set to 6 type @ 33 +MTRR addr 0xca-0xcb set to 6 type @ 34 +MTRR addr 0xcb-0xcc set to 6 type @ 35 +MTRR addr 0xcc-0xcd set to 6 type @ 36 +MTRR addr 0xcd-0xce set to 6 type @ 37 +MTRR addr 0xce-0xcf set to 6 type @ 38 +MTRR addr 0xcf-0xd0 set to 6 type @ 39 +MTRR addr 0xd0-0xd1 set to 6 type @ 40 +MTRR addr 0xd1-0xd2 set to 6 type @ 41 +MTRR addr 0xd2-0xd3 set to 6 type @ 42 +MTRR addr 0xd3-0xd4 set to 6 type @ 43 +MTRR addr 0xd4-0xd5 set to 6 type @ 44 +MTRR addr 0xd5-0xd6 set to 6 type @ 45 +MTRR addr 0xd6-0xd7 set to 6 type @ 46 +MTRR addr 0xd7-0xd8 set to 6 type @ 47 +MTRR addr 0xd8-0xd9 set to 6 type @ 48 +MTRR addr 0xd9-0xda set to 6 type @ 49 +MTRR addr 0xda-0xdb set to 6 type @ 50 +MTRR addr 0xdb-0xdc set to 6 type @ 51 +MTRR addr 0xdc-0xdd set to 6 type @ 52 +MTRR addr 0xdd-0xde set to 6 type @ 53 +MTRR addr 0xde-0xdf set to 6 type @ 54 +MTRR addr 0xdf-0xe0 set to 6 type @ 55 +MTRR addr 0xe0-0xe1 set to 6 type @ 56 +MTRR addr 0xe1-0xe2 set to 6 type @ 57 +MTRR addr 0xe2-0xe3 set to 6 type @ 58 +MTRR addr 0xe3-0xe4 set to 6 type @ 59 +MTRR addr 0xe4-0xe5 set to 6 type @ 60 +MTRR addr 0xe5-0xe6 set to 6 type @ 61 +MTRR addr 0xe6-0xe7 set to 6 type @ 62 +MTRR addr 0xe7-0xe8 set to 6 type @ 63 +MTRR addr 0xe8-0xe9 set to 6 type @ 64 +MTRR addr 0xe9-0xea set to 6 type @ 65 +MTRR addr 0xea-0xeb set to 6 type @ 66 +MTRR addr 0xeb-0xec set to 6 type @ 67 +MTRR addr 0xec-0xed set to 6 type @ 68 +MTRR addr 0xed-0xee set to 6 type @ 69 +MTRR addr 0xee-0xef set to 6 type @ 70 +MTRR addr 0xef-0xf0 set to 6 type @ 71 +MTRR addr 0xf0-0xf1 set to 6 type @ 72 +MTRR addr 0xf1-0xf2 set to 6 type @ 73 +MTRR addr 0xf2-0xf3 set to 6 type @ 74 +MTRR addr 0xf3-0xf4 set to 6 type @ 75 +MTRR addr 0xf4-0xf5 set to 6 type @ 76 +MTRR addr 0xf5-0xf6 set to 6 type @ 77 +MTRR addr 0xf6-0xf7 set to 6 type @ 78 +MTRR addr 0xf7-0xf8 set to 6 type @ 79 +MTRR addr 0xf8-0xf9 set to 6 type @ 80 +MTRR addr 0xf9-0xfa set to 6 type @ 81 +MTRR addr 0xfa-0xfb set to 6 type @ 82 +MTRR addr 0xfb-0xfc set to 6 type @ 83 +MTRR addr 0xfc-0xfd set to 6 type @ 84 +MTRR addr 0xfd-0xfe set to 6 type @ 85 +MTRR addr 0xfe-0xff set to 6 type @ 86 +MTRR addr 0xff-0x100 set to 6 type @ 87 +MTRR: Fixed MSR 0x250 0x0606060606060606 +MTRR: Fixed MSR 0x258 0x0606060606060606 +MTRR: Fixed MSR 0x259 0x0000000000000000 +MTRR: Fixed MSR 0x268 0x0606060606060606 +MTRR: Fixed MSR 0x269 0x0606060606060606 +MTRR: Fixed MSR 0x26a 0x0606060606060606 +MTRR: Fixed MSR 0x26b 0x0606060606060606 +MTRR: Fixed MSR 0x26c 0x0606060606060606 +MTRR: Fixed MSR 0x26d 0x0606060606060606 +MTRR: Fixed MSR 0x26e 0x0606060606060606 +MTRR: Fixed MSR 0x26f 0x0606060606060606 +call enable_fixed_mtrr() +CPU physical address size: 32 bits +MTRR: default type WB/UC MTRR counts: 4/4. +MTRR: UC selected as default type. +MTRR: 0 base 0x0000000000000000 mask 0x0000000080000000 type 6 +MTRR: 1 base 0x0000000080000000 mask 0x00000000c0000000 type 6 +MTRR: 2 base 0x00000000bf800000 mask 0x00000000ff800000 type 0 +MTRR: 3 base 0x00000000d0000000 mask 0x00000000f0000000 type 1 + +MTRR check +Fixed MTRRs : Enabled +Variable MTRRs: Enabled + +Setting up local apic... apic_id: 0x00 done. +CPU: 0 2 siblings +CPU: 0 has sibling 1 +CPU #0 initialized +CPU1: stack_base 0014a000, stack_end 0014aff8 +Asserting INIT. +Waiting for send to finish... ++Deasserting INIT. +Waiting for send to finish... ++#startup loops: 2. +Sending STARTUP #1 to 1. +After apic_write. +Startup point 1. +Waiting for send to finish... ++Sending STARTUP #2 to 1. +After apic_write. +Startup point 1. +Waiting for send to finish... ++After Startup. +Initializing CPU #1 +Waiting for 1 CPUS to stop +CPU: vendor Intel device 6ec +CPU: family 06, model 0e, stepping 0c +Enabling cache +microcode: sig=0x6ec pf=0x20 revision=0x0 +Microcode size field is 0 +Microcode size field is 0 +Microcode size field is 0 +Microcode size field is 0 +microcode: updated to revision 0x54 date=2006-05-01 +CPU: Intel(R) Core(TM) Duo CPU L2400 @ 1.66GHz. +MTRR: Fixed MSR 0x250 0x0606060606060606 +MTRR: Fixed MSR 0x258 0x0606060606060606 +MTRR: Fixed MSR 0x259 0x0000000000000000 +MTRR: Fixed MSR 0x268 0x0606060606060606 +MTRR: Fixed MSR 0x269 0x0606060606060606 +MTRR: Fixed MSR 0x26a 0x0606060606060606 +MTRR: Fixed MSR 0x26b 0x0606060606060606 +MTRR: Fixed MSR 0x26c 0x0606060606060606 +MTRR: Fixed MSR 0x26d 0x0606060606060606 +MTRR: Fixed MSR 0x26e 0x0606060606060606 +MTRR: Fixed MSR 0x26f 0x0606060606060606 +call enable_fixed_mtrr() +CPU physical address size: 32 bits +MTRR: 0 base 0x0000000000000000 mask 0x0000000080000000 type 6 +MTRR: 1 base 0x0000000080000000 mask 0x00000000c0000000 type 6 +MTRR: 2 base 0x00000000bf800000 mask 0x00000000ff800000 type 0 +MTRR: 3 base 0x00000000d0000000 mask 0x00000000f0000000 type 1 + +MTRR check +Fixed MTRRs : Enabled +Variable MTRRs: Enabled + +Setting up local apic... apic_id: 0x01 done. +CPU: 1 2 siblings +CPU #1 initialized +CPU 1 going down... +All AP CPUs stopped (11642 loops) +CPU1: stack: 0014a000 - 0014b000, lowest used address 0014ac68, stack used: 920 bytes +CPU_CLUSTER: 0 init 687602 usecs +PCI: 00:00.0 init +Normal boot. +PCI: 00:00.0 init 2905 usecs +PCI: 00:02.0 init +In CBFS, ROM address for PCI: 00:02.0 = ffe007b8 +PCI expansion ROM, signature 0xaa55, INIT size 0x10000, data ptr 0x0040 +PCI ROM image, vendor ID 8086, device ID 27a2, +PCI ROM image, Class Code 030000, Code Type 00 +Copying VGA ROM Image from ffe007b8 to 0xc0000, 0x10000 bytes +Real mode stub @00000600: 867 bytes +Calling Option ROM... +int15_handler: AX=5f40 BX=d103 CX=0055 DX=0002 +DISPLAY=3 +int15_handler: AX=5f34 BX=078f CX=0002 DX=0002 +Unknown INT15 function 5f34! +int15 call returned error. +int15_handler: AX=5f35 BX=078f CX=0002 DX=00c0 +... Option ROM returned. +VGA Option ROM was run +gma_func0_init: After VBIOS/native init: GMADR=0xd0000008 GTTADR=0xe4400000 +PCI: 00:02.0 init 175395 usecs +PCI: 00:02.1 init +PCI: 00:02.1 init 2383 usecs +PCI: 00:1b.0 init +Azalia: codec type: Azalia +Azalia: base = e4440000 +Azalia: codec_mask = 03 +Azalia: Initializing codec #1 +Azalia: codec viddid: 14f12bfa +Azalia: No verb! +Azalia: Initializing codec #0 +Azalia: codec viddid: 11d41981 +Azalia: No verb! +PCI: 00:1b.0 init 25808 usecs +PCI: 00:1c.0 init +Initializing ICH7 PCIe bridge. +PCI: 00:1c.0 init 4491 usecs +PCI: 00:1c.1 init +Initializing ICH7 PCIe bridge. +PCI: 00:1c.1 init 4490 usecs +PCI: 00:1c.2 init +Initializing ICH7 PCIe bridge. +PCI: 00:1c.2 init 4491 usecs +PCI: 00:1c.3 init +Initializing ICH7 PCIe bridge. +PCI: 00:1c.3 init 4491 usecs +PCI: 00:1d.0 init +UHCI: Setting up controller.. done. +PCI: 00:1d.0 init 4923 usecs +PCI: 00:1d.1 init +UHCI: Setting up controller.. done. +PCI: 00:1d.1 init 4924 usecs +PCI: 00:1d.2 init +UHCI: Setting up controller.. done. +PCI: 00:1d.2 init 4924 usecs +PCI: 00:1d.3 init +UHCI: Setting up controller.. done. +PCI: 00:1d.3 init 4925 usecs +PCI: 00:1d.7 init +EHCI: Setting up controller.. done. +PCI: 00:1d.7 init 4933 usecs +PCI: 00:1e.0 init +PCI: 00:1e.0 init 1681 usecs +PCI: 00:1f.0 init +i82801gx: lpc_init +IOAPIC: Initializing IOAPIC at 0xfec00000 +IOAPIC: Bootstrap Processor Local APIC = 0x00 +IOAPIC: ID = 0x02 +IOAPIC: Dumping registers + reg 0x0000: 0x02000000 + reg 0x0001: 0x00170020 + reg 0x0002: 0x00170020 +WARNING: No CMOS option 'power_on_after_fail'. +Set power on after power failure. +NMI sources enabled. +rtc_failed = 0x0 +RTC Init +i8259_configure_irq_trigger: current interrupts are 0x0 +i8259_configure_irq_trigger: try to set interrupts 0x200 +Disabling ACPI via APMC: +done. +Locking SMM. +PCI: 00:1f.0 init 50464 usecs +PCI: 00:1f.1 init +i82801gx_ide: initializing... IDE0 +PCI: 00:1f.1 init 4941 usecs +PCI: 00:1f.2 init +i82801gx_sata: initializing... +SATA controller in AHCI mode. +PCI: 00:1f.2 init 7211 usecs +PCI: 01:00.0 init +PCI: 01:00.0 init 1668 usecs +PCI: 02:00.0 init +PCI: 02:00.0 init 1670 usecs +PCI: 05:00.0 init +Ricoh RL5c476: Initializing. +CF Base = 0 +CF boot not enabled. +PCI: 05:00.0 init 7378 usecs +PCI: 05:00.1 init +PCI: 05:00.1 init 1669 usecs +PCI: 05:00.2 init +PCI: 05:00.2 init 1671 usecs +PCI: 05:00.3 init +PCI: 05:00.3 init 1671 usecs +PNP: 164e.2 init +PNP: 164e.2 init 1584 usecs +PNP: 164e.7 init +PNP: 164e.7 init 1583 usecs +PNP: 164e.19 init +PNP: 164e.19 init 1670 usecs +PNP: 002e.1 init +PNP: 002e.1 init 1582 usecs +PNP: 002e.3 init +PNP: 002e.3 init 1583 usecs +PNP: 002e.7 init +PNP: 002e.7 init 1582 usecs +smbus: PCI: 00:1f.3[0]->I2C: 01:69 init +I2C: 01:69 init 16211 usecs +smbus: PCI: 00:1f.3[0]->I2C: 01:54 init +I2C: 01:54 init 3591 usecs +smbus: PCI: 00:1f.3[0]->I2C: 01:55 init +I2C: 01:55 init 3592 usecs +smbus: PCI: 00:1f.3[0]->I2C: 01:56 init +I2C: 01:56 init 3593 usecs +smbus: PCI: 00:1f.3[0]->I2C: 01:57 init +I2C: 01:57 init 3592 usecs +smbus: PCI: 00:1f.3[0]->I2C: 01:5c init +Locking EEPROM RFID +init EEPROM done +I2C: 01:5c init 28615 usecs +smbus: PCI: 00:1f.3[0]->I2C: 01:5d init +I2C: 01:5d init 3593 usecs +smbus: PCI: 00:1f.3[0]->I2C: 01:5e init +I2C: 01:5e init 3593 usecs +smbus: PCI: 00:1f.3[0]->I2C: 01:5f init +I2C: 01:5f init 3592 usecs +Devices initialized +Show all devs...After init. +Root Device: enabled 1 +CPU_CLUSTER: 0: enabled 1 +APIC: 00: enabled 1 +DOMAIN: 0000: enabled 1 +PCI: 00:00.0: enabled 1 +PCI: 00:02.0: enabled 1 +PCI: 00:02.1: enabled 1 +PCI: 00:1b.0: enabled 1 +PCI: 00:1c.0: enabled 1 +PCI: 00:1c.1: enabled 1 +PCI: 00:1d.0: enabled 1 +PCI: 00:1d.1: enabled 1 +PCI: 00:1d.2: enabled 1 +PCI: 00:1d.3: enabled 1 +PCI: 00:1d.7: enabled 1 +PCI: 00:1f.0: enabled 1 +PNP: 00ff.1: enabled 1 +PNP: 00ff.2: enabled 1 +PNP: 164e.2: enabled 1 +PNP: 164e.3: enabled 0 +PNP: 164e.7: enabled 1 +PNP: 164e.19: enabled 1 +PNP: 002e.0: enabled 0 +PNP: 002e.1: enabled 1 +PNP: 002e.2: enabled 0 +PNP: 002e.3: enabled 1 +PNP: 002e.7: enabled 1 +PNP: 002e.a: enabled 0 +PCI: 00:1f.1: enabled 1 +PCI: 00:1f.2: enabled 1 +PCI: 00:1f.3: enabled 1 +I2C: 01:69: enabled 1 +I2C: 01:54: enabled 1 +I2C: 01:55: enabled 1 +I2C: 01:56: enabled 1 +I2C: 01:57: enabled 1 +I2C: 01:5c: enabled 1 +I2C: 01:5d: enabled 1 +I2C: 01:5e: enabled 1 +I2C: 01:5f: enabled 1 +PCI: 00:1c.2: enabled 1 +PCI: 00:1c.3: enabled 1 +PCI: 00:1e.0: enabled 1 +PCI: 01:00.0: enabled 1 +PCI: 02:00.0: enabled 1 +PCI: 05:00.0: enabled 1 +PCI: 05:00.1: enabled 1 +PCI: 05:00.2: enabled 1 +PCI: 05:00.3: enabled 1 +APIC: 01: enabled 1 +BS: Exiting BS_DEV_INIT state. +BS: BS_DEV_INIT times (us): entry 0 run 1321463 exit 0 +BS: Entering BS_POST_DEVICE state. +CBMEM region bf6d0000-bf7fffff (cbmem_check_toc) +Adding CBMEM entry as no. 4 +Moving GDT to bf6e0600...ok +Finalize devices... +Devices finalized +BS: Exiting BS_POST_DEVICE state. +BS: BS_POST_DEVICE times (us): entry 9470 run 6558 exit 0 +BS: Entering BS_OS_RESUME_CHECK state. +BS: Exiting BS_OS_RESUME_CHECK state. +BS: BS_OS_RESUME_CHECK times (us): entry 0 run 3401 exit 0 +BS: Entering BS_WRITE_TABLES state. +Copying Interrupt Routing Table to 0x000f0000... done. +Adding CBMEM entry as no. 5 +Copying Interrupt Routing Table to 0xbf6e0800... done. +PIRQ table: 272 bytes. +Wrote the mp table end at: 000f0410 - 000f05cc +Adding CBMEM entry as no. 6 +Wrote the mp table end at: bf6e1810 - bf6e19cc +MP table: 460 bytes. +Adding CBMEM entry as no. 7 +ACPI: Writing ACPI tables at bf6e2800. +ACPI: * HPET +ACPI: added table 1/32, length now 40 +ACPI: * MADT +ACPI: added table 2/32, length now 44 +ACPI: * MCFG +ACPI: added table 3/32, length now 48 +ACPI: * FACS +ACPI: Patching up global NVS in DSDT at offset 0x0263 -> 0xbf6e5c10 +ACPI: * DSDT @ bf6e2b40 Length 30ca +ACPI: * FADT +ACPI: added table 4/32, length now 52 +ACPI: * SSDT +Found 1 CPU(s) with 2 core(s) each. +clocks between 1000 and 1666 MHz. +adding 3 P-States between busratio 6 and a, incl. P0 +PSS: 1666MHz power 31000 control 0xa1e status 0xa1e +PSS: 1333MHz power 22050 control 0x818 status 0x818 +PSS: 1000MHz power 13100 control 0x613 status 0x613 +clocks between 1000 and 1666 MHz. +adding 3 P-States between busratio 6 and a, incl. P0 +PSS: 1666MHz power 31000 control 0xa1e status 0xa1e +PSS: 1333MHz power 22050 control 0x818 status 0x818 +PSS: 1000MHz power 13100 control 0x613 status 0x613 +ACPI: added table 5/32, length now 56 +current = bf6e6110 +ACPI: done. +Laptop handling... +ACPI tables: 14608 bytes. +Adding CBMEM entry as no. 8 +smbios_write_tables: bf6edc00 +Root Device (Lenovo ThinkPad X60 / X60s) +recv_ec_data: 0x37 +recv_ec_data: 0x42 +recv_ec_data: 0x48 +recv_ec_data: 0x54 +recv_ec_data: 0x33 +recv_ec_data: 0x37 +recv_ec_data: 0x57 +recv_ec_data: 0x57 +recv_ec_data: 0x04 +recv_ec_data: 0x03 +CPU_CLUSTER: 0 (Intel i945 Northbridge) +APIC: 00 (Socket mFCPGA478 CPU) +DOMAIN: 0000 (Intel i945 Northbridge) +PCI: 00:00.0 (Intel i945 Northbridge) +PCI: 00:02.0 (Intel i945 Northbridge) +PCI: 00:02.1 (Intel i945 Northbridge) +PCI: 00:1b.0 (Intel ICH7/ICH7-M (82801Gx) Series Southbridge) +PCI: 00:1c.0 (Intel ICH7/ICH7-M (82801Gx) Series Southbridge) +PCI: 00:1c.1 (Intel ICH7/ICH7-M (82801Gx) Series Southbridge) +PCI: 00:1d.0 (Intel ICH7/ICH7-M (82801Gx) Series Southbridge) +PCI: 00:1d.1 (Intel ICH7/ICH7-M (82801Gx) Series Southbridge) +PCI: 00:1d.2 (Intel ICH7/ICH7-M (82801Gx) Series Southbridge) +PCI: 00:1d.3 (Intel ICH7/ICH7-M (82801Gx) Series Southbridge) +PCI: 00:1d.7 (Intel ICH7/I +4509 bytes lost diff --git a/docs/future/dumps/coreboot_5926_oprom_grub_config b/docs/future/dumps/coreboot_5926_oprom_grub_config @@ -0,0 +1,449 @@ +# +# Automatically generated file; DO NOT EDIT. +# coreboot configuration +# + +# +# General setup +# +CONFIG_EXPERT=y +CONFIG_LOCALVERSION="7BETC7WW (2.08 )" +CONFIG_CBFS_PREFIX="fallback" +CONFIG_COMPILER_GCC=y +# CONFIG_COMPILER_LLVM_CLANG is not set +# CONFIG_ANY_TOOLCHAIN is not set +# CONFIG_CCACHE is not set +# CONFIG_SCONFIG_GENPARSER is not set +CONFIG_USE_OPTION_TABLE=y +CONFIG_COMPRESS_RAMSTAGE=y +CONFIG_INCLUDE_CONFIG_FILE=y +CONFIG_EARLY_CBMEM_INIT=y +# CONFIG_BROKEN_CAR_MIGRATE is not set +# CONFIG_DYNAMIC_CBMEM is not set +# CONFIG_COLLECT_TIMESTAMPS is not set +# CONFIG_USE_BLOBS is not set +# CONFIG_COVERAGE is not set + +# +# Mainboard +# +# CONFIG_VENDOR_AAEON is not set +# CONFIG_VENDOR_ABIT is not set +# CONFIG_VENDOR_ADLINK is not set +# CONFIG_VENDOR_ADVANSUS is not set +# CONFIG_VENDOR_ADVANTECH is not set +# CONFIG_VENDOR_AMD is not set +# CONFIG_VENDOR_AOPEN is not set +# CONFIG_VENDOR_ARIMA is not set +# CONFIG_VENDOR_ARTECGROUP is not set +# CONFIG_VENDOR_ASI is not set +# CONFIG_VENDOR_ASROCK is not set +# CONFIG_VENDOR_ASUS is not set +# CONFIG_VENDOR_A_TREND is not set +# CONFIG_VENDOR_AVALUE is not set +# CONFIG_VENDOR_AXUS is not set +# CONFIG_VENDOR_AZZA is not set +# CONFIG_VENDOR_BACHMANN is not set +# CONFIG_VENDOR_BCOM is not set +# CONFIG_VENDOR_BIFFEROS is not set +# CONFIG_VENDOR_BIOSTAR is not set +# CONFIG_VENDOR_BROADCOM is not set +# CONFIG_VENDOR_COMPAQ is not set +# CONFIG_VENDOR_CUBIETECH is not set +# CONFIG_VENDOR_DIGITALLOGIC is not set +# CONFIG_VENDOR_DMP is not set +# CONFIG_VENDOR_EAGLELION is not set +# CONFIG_VENDOR_ECS is not set +# CONFIG_VENDOR_EMULATION is not set +# CONFIG_VENDOR_GETAC is not set +# CONFIG_VENDOR_GIGABYTE is not set +# CONFIG_VENDOR_GIZMOSPHERE is not set +# CONFIG_VENDOR_GOOGLE is not set +# CONFIG_VENDOR_HP is not set +# CONFIG_VENDOR_IBASE is not set +# CONFIG_VENDOR_IBM is not set +# CONFIG_VENDOR_IEI is not set +# CONFIG_VENDOR_INTEL is not set +# CONFIG_VENDOR_IWAVE is not set +# CONFIG_VENDOR_IWILL is not set +# CONFIG_VENDOR_JETWAY is not set +# CONFIG_VENDOR_KONTRON is not set +# CONFIG_VENDOR_LANNER is not set +CONFIG_VENDOR_LENOVO=y +# CONFIG_VENDOR_LINUTOP is not set +# CONFIG_VENDOR_LIPPERT is not set +# CONFIG_VENDOR_MITAC is not set +# CONFIG_VENDOR_MSI is not set +# CONFIG_VENDOR_NEC is not set +# CONFIG_VENDOR_NEWISYS is not set +# CONFIG_VENDOR_NOKIA is not set +# CONFIG_VENDOR_NVIDIA is not set +# CONFIG_VENDOR_PACKARDBELL is not set +# CONFIG_VENDOR_PCENGINES is not set +# CONFIG_VENDOR_RCA is not set +# CONFIG_VENDOR_RODA is not set +# CONFIG_VENDOR_SAMSUNG is not set +# CONFIG_VENDOR_SIEMENS is not set +# CONFIG_VENDOR_SOYO is not set +# CONFIG_VENDOR_SUNW is not set +# CONFIG_VENDOR_SUPERMICRO is not set +# CONFIG_VENDOR_TECHNEXION is not set +# CONFIG_VENDOR_TECHNOLOGIC is not set +# CONFIG_VENDOR_TELEVIDEO is not set +# CONFIG_VENDOR_TI is not set +# CONFIG_VENDOR_THOMSON is not set +# CONFIG_VENDOR_TRAVERSE is not set +# CONFIG_VENDOR_TYAN is not set +# CONFIG_VENDOR_VIA is not set +# CONFIG_VENDOR_WINENT is not set +# CONFIG_VENDOR_WYSE is not set +CONFIG_BOARD_SPECIFIC_OPTIONS=y +CONFIG_MAINBOARD_DIR="lenovo/x60" +CONFIG_MAINBOARD_PART_NUMBER="ThinkPad X60 / X60s" +CONFIG_IRQ_SLOT_COUNT=18 +CONFIG_MAINBOARD_VENDOR="Lenovo" +CONFIG_MAX_CPUS=2 +CONFIG_RAMTOP=0x200000 +CONFIG_HEAP_SIZE=0x4000 +CONFIG_RAMBASE=0x100000 +CONFIG_VGA_BIOS_ID="8086,27a2" +CONFIG_DRIVERS_PS2_KEYBOARD=y +# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set +CONFIG_VGA_BIOS=y +# CONFIG_UDELAY_IO is not set +CONFIG_DCACHE_RAM_BASE=0xffdf8000 +CONFIG_DCACHE_RAM_SIZE=0x8000 +CONFIG_ACPI_SSDTX_NUM=0 +CONFIG_VGA_BIOS_FILE="vgabios.bin" +# CONFIG_PCI_64BIT_PREF_MEM is not set +CONFIG_MMCONF_BASE_ADDRESS=0xf0000000 +CONFIG_UART_FOR_CONSOLE=0 +CONFIG_ID_SECTION_OFFSET=0x80 +CONFIG_STACK_SIZE=0x1000 +CONFIG_CACHE_ROM_SIZE_OVERRIDE=0 +CONFIG_CBFS_SIZE=0x200000 +CONFIG_BOARD_LENOVO_X60=y +# CONFIG_BOARD_LENOVO_X201 is not set +# CONFIG_BOARD_LENOVO_X230 is not set +# CONFIG_BOARD_LENOVO_T520 is not set +# CONFIG_BOARD_LENOVO_T530 is not set +# CONFIG_BOARD_LENOVO_T60 is not set +CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="LENOVO" +CONFIG_SEABIOS_PS2_TIMEOUT=3000 +CONFIG_MAINBOARD_VERSION="ThinkPad X60" +CONFIG_CPU_ADDR_BITS=32 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 +# CONFIG_USBDEBUG is not set +CONFIG_MAXIMUM_SUPPORTED_FREQUENCY=0 +CONFIG_BOARD_ROMSIZE_KB_2048=y +# CONFIG_COREBOOT_ROMSIZE_KB_64 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_128 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set +CONFIG_COREBOOT_ROMSIZE_KB_2048=y +# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_8192 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set +CONFIG_COREBOOT_ROMSIZE_KB=2048 +CONFIG_ROM_SIZE=0x200000 +CONFIG_MAINBOARD_SERIAL_NUMBER="L3AZ921" +CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="1703WMF" +CONFIG_ARCH_X86=y +# CONFIG_ARCH_ARMV7 is not set +CONFIG_ARCH_BOOTBLOCK_X86_32=y +CONFIG_ARCH_ROMSTAGE_X86_32=y +CONFIG_ARCH_RAMSTAGE_X86_32=y +CONFIG_AP_IN_SIPI_WAIT=y +# CONFIG_SIPI_VECTOR_IN_ROM is not set +CONFIG_NUM_IPI_STARTS=2 +# CONFIG_ROMCC is not set +CONFIG_PC80_SYSTEM=y +CONFIG_BOOTBLOCK_NORTHBRIDGE_INIT="northbridge/intel/i945/bootblock.c" +CONFIG_HAVE_CMOS_DEFAULT=y +CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default" +CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT="southbridge/intel/i82801gx/bootblock.c" +CONFIG_IOAPIC_INTERRUPTS_ON_FSB=y +# CONFIG_IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS is not set +CONFIG_HPET_ADDRESS=0xfed00000 +# CONFIG_ARCH_BOOTBLOCK_ARMV7 is not set +# CONFIG_ARCH_ROMSTAGE_ARMV7 is not set +# CONFIG_ARCH_RAMSTAGE_ARMV7 is not set +# CONFIG_MAINBOARD_HAS_CHROMEOS is not set +CONFIG_BOOTBLOCK_SIMPLE=y +# CONFIG_BOOTBLOCK_NORMAL is not set +CONFIG_BOOTBLOCK_SOURCE="bootblock_simple.c" +# CONFIG_UPDATE_IMAGE is not set + +# +# Chipset +# + +# +# CPU +# +# CONFIG_CPU_ALLWINNER_A10 is not set +# CONFIG_CPU_ARMLTD_CORTEX_A9 is not set +# CONFIG_CPU_SAMSUNG_EXYNOS5250 is not set +# CONFIG_CPU_SAMSUNG_EXYNOS5420 is not set +# CONFIG_CPU_TI_AM335X is not set +CONFIG_SOCKET_SPECIFIC_OPTIONS=y +CONFIG_XIP_ROM_SIZE=0x10000 +# CONFIG_CPU_AMD_AGESA is not set +CONFIG_HIGH_SCRATCH_MEMORY_SIZE=0x0 +CONFIG_CPU_INTEL_MODEL_6EX=y +CONFIG_CPU_INTEL_MODEL_6FX=y +CONFIG_SMM_TSEG_SIZE=0 +CONFIG_CPU_INTEL_SOCKET_MFCPGA478=y +CONFIG_SSE2=y +# CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE is not set +# CONFIG_CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED is not set +# CONFIG_PARALLEL_CPU_INIT is not set +CONFIG_UDELAY_LAPIC=y +CONFIG_LAPIC_MONOTONIC_TIMER=y +# CONFIG_UDELAY_TSC is not set +# CONFIG_UDELAY_TIMER2 is not set +# CONFIG_TSC_CALIBRATE_WITH_IO is not set +# CONFIG_TSC_SYNC_LFENCE is not set +CONFIG_TSC_SYNC_MFENCE=y +CONFIG_LOGICAL_CPUS=y +# CONFIG_SMM_TSEG is not set +# CONFIG_SMM_MODULES is not set +# CONFIG_X86_AMD_FIXED_MTRRS is not set +# CONFIG_PLATFORM_USES_FSP is not set +# CONFIG_PARALLEL_MP is not set +# CONFIG_BACKUP_DEFAULT_SMM_REGION is not set +# CONFIG_MIRROR_PAYLOAD_TO_RAM_BEFORE_LOADING is not set +CONFIG_CACHE_AS_RAM=y +CONFIG_SMP=y +CONFIG_AP_SIPI_VECTOR=0xfffff000 +CONFIG_MMX=y +CONFIG_SSE=y +CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y +CONFIG_CPU_MICROCODE_ADDED_DURING_BUILD=y +CONFIG_CPU_MICROCODE_CBFS_GENERATE=y +# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL is not set +# CONFIG_CPU_MICROCODE_CBFS_NONE is not set + +# +# Northbridge +# +CONFIG_VIDEO_MB=0 +# CONFIG_NORTHBRIDGE_AMD_AGESA is not set +CONFIG_S3_VGA_ROM_RUN=y +# CONFIG_AMD_NB_CIMX is not set +# CONFIG_NORTHBRIDGE_AMD_CIMX_RD890 is not set +CONFIG_NORTHBRIDGE_SPECIFIC_OPTIONS=y +CONFIG_NORTHBRIDGE_INTEL_I945=y +# CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GC is not set +CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM=y +CONFIG_CHANNEL_XOR_RANDOMIZATION=y +# CONFIG_OVERRIDE_CLOCK_DISABLE is not set +# CONFIG_CHECK_SLFRCS_ON_RESUME is not set +CONFIG_HPET_MIN_TICKS=0x80 +CONFIG_MAX_PIRQ_LINKS=4 + +# +# Southbridge +# +CONFIG_EHCI_BAR=0xfef00000 +# CONFIG_AMD_SB_CIMX is not set +# CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800 is not set +# CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900 is not set +CONFIG_SOUTHBRIDGE_INTEL_COMMON=y +CONFIG_SOUTHBRIDGE_INTEL_I82801GX=y +CONFIG_SOUTHBRIDGE_RICOH_RL5C476=y + +# +# Super I/O +# +CONFIG_SUPERIO_NSC_PC87382=y +CONFIG_SUPERIO_NSC_PC87392=y + +# +# Embedded Controllers +# +CONFIG_EC_ACPI=y +CONFIG_EC_LENOVO_H8=y +CONFIG_H8_DOCK_EARLY_INIT=y +CONFIG_EC_LENOVO_PMH7=y + +# +# SoC +# + +# +# Devices +# +CONFIG_MAINBOARD_HAS_NATIVE_VGA_INIT=y +# CONFIG_MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG is not set +# CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT is not set +CONFIG_VGA_ROM_RUN=y +# CONFIG_ALWAYS_LOAD_OPROM is not set +CONFIG_ON_DEVICE_ROM_RUN=y +CONFIG_PCI_OPTION_ROM_RUN_REALMODE=y +# CONFIG_PCI_OPTION_ROM_RUN_YABEL is not set +# CONFIG_MULTIPLE_VGA_ADAPTERS is not set +CONFIG_PCI=y +# CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT is not set +CONFIG_PCIX_PLUGIN_SUPPORT=y +CONFIG_PCIEXP_PLUGIN_SUPPORT=y +CONFIG_AGP_PLUGIN_SUPPORT=y +CONFIG_CARDBUS_PLUGIN_SUPPORT=y +# CONFIG_AZALIA_PLUGIN_SUPPORT is not set +# CONFIG_PCIEXP_COMMON_CLOCK is not set +# CONFIG_PCIEXP_ASPM is not set +CONFIG_PCI_BUS_SEGN_BITS=0 +# CONFIG_EARLY_PCI_BRIDGE is not set + +# +# VGA BIOS +# + +# +# Display +# +# CONFIG_FRAMEBUFFER_SET_VESA_MODE is not set +# CONFIG_FRAMEBUFFER_KEEP_VESA_MODE is not set + +# +# PXE ROM +# +# CONFIG_PXE_ROM is not set +CONFIG_SUBSYSTEM_VENDOR_ID=0x0000 +CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 + +# +# Generic Drivers +# +# CONFIG_DRIVERS_I2C_RTD2132 is not set +CONFIG_DRIVERS_ICS_954309=y +# CONFIG_INTEL_DP is not set +# CONFIG_INTEL_DDI is not set +# CONFIG_INTEL_EDID is not set +# CONFIG_IPMI_KCS is not set +# CONFIG_DRIVER_MAXIM_MAX77686 is not set +# CONFIG_DRIVER_PARADE_PS8625 is not set +# CONFIG_TPM is not set +# CONFIG_DRIVERS_SIL_3114 is not set +# CONFIG_SPI_FLASH is not set +# CONFIG_DRIVER_TI_TPS65090 is not set +CONFIG_DRIVERS_UART=y +CONFIG_DRIVERS_UART_8250IO=y +# CONFIG_NO_UART_ON_SUPERIO is not set +# CONFIG_DRIVERS_UART_8250MEM is not set +# CONFIG_HAVE_UART_SPECIAL is not set +# CONFIG_DRIVERS_UART_OXPCIE is not set +# CONFIG_DRIVERS_UART_PL011 is not set +CONFIG_HAVE_USBDEBUG=y +# CONFIG_HAVE_USBDEBUG_OPTIONS is not set +# CONFIG_DRIVER_XPOWERS_AXP209 is not set +CONFIG_MMCONF_SUPPORT_DEFAULT=y +CONFIG_MMCONF_SUPPORT=y +# CONFIG_BOOTMODE_STRAPS is not set + +# +# Console +# +CONFIG_SQUELCH_EARLY_SMP=y +CONFIG_CONSOLE_SERIAL=y + +# +# I/O mapped, 8250-compatible +# +CONFIG_TTYS0_BASE=0x3f8 +CONFIG_CONSOLE_SERIAL_115200=y +# CONFIG_CONSOLE_SERIAL_57600 is not set +# CONFIG_CONSOLE_SERIAL_38400 is not set +# CONFIG_CONSOLE_SERIAL_19200 is not set +# CONFIG_CONSOLE_SERIAL_9600 is not set +CONFIG_TTYS0_BAUD=115200 +CONFIG_TTYS0_LCS=3 +# CONFIG_SPKMODEM is not set +# CONFIG_CONSOLE_NE2K is not set +CONFIG_CONSOLE_CBMEM=y +CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x10000 +CONFIG_CONSOLE_CAR_BUFFER_SIZE=0xc00 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8=y +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set +# CONFIG_NO_POST is not set +# CONFIG_CMOS_POST is not set +# CONFIG_POST_IO is not set +CONFIG_POST_DEVICE=y +CONFIG_POST_DEVICE_NONE=y +# CONFIG_POST_DEVICE_LPC is not set +# CONFIG_POST_DEVICE_PCI_PCIE is not set +CONFIG_HAVE_ACPI_RESUME=y +# CONFIG_HAVE_ACPI_SLIC is not set +CONFIG_HAVE_HARD_RESET=y +CONFIG_HAVE_MONOTONIC_TIMER=y +# CONFIG_TIMER_QUEUE is not set +CONFIG_HAVE_OPTION_TABLE=y +# CONFIG_PIRQ_ROUTE is not set +CONFIG_HAVE_SMI_HANDLER=y +# CONFIG_PCI_IO_CFG_EXT is not set +CONFIG_IOAPIC=y +CONFIG_USE_WATCHDOG_ON_BOOT=y +# CONFIG_VGA is not set +# CONFIG_GFXUMA is not set +# CONFIG_RELOCATABLE_MODULES is not set +# CONFIG_HAVE_REFCODE_BLOB is not set +CONFIG_HAVE_ACPI_TABLES=y +CONFIG_HAVE_MP_TABLE=y +CONFIG_HAVE_PIRQ_TABLE=y + +# +# System tables +# +CONFIG_GENERATE_ACPI_TABLES=y +CONFIG_GENERATE_MP_TABLE=y +CONFIG_GENERATE_PIRQ_TABLE=y +CONFIG_GENERATE_SMBIOS_TABLES=y + +# +# Payload +# +# CONFIG_PAYLOAD_NONE is not set +CONFIG_PAYLOAD_ELF=y +# CONFIG_PAYLOAD_LINUX is not set +# CONFIG_PAYLOAD_SEABIOS is not set +# CONFIG_PAYLOAD_FILO is not set +# CONFIG_PAYLOAD_GRUB2 is not set +# CONFIG_PAYLOAD_TIANOCORE is not set +# CONFIG_SEABIOS_THREAD_OPTIONROMS is not set +CONFIG_PAYLOAD_FILE="grub.elf" +CONFIG_COMPRESSED_PAYLOAD_LZMA=y + +# +# Debugging +# +# CONFIG_GDB_STUB is not set +# CONFIG_DEBUG_CBFS is not set +CONFIG_HAVE_DEBUG_RAM_SETUP=y +# CONFIG_DEBUG_RAM_SETUP is not set +# CONFIG_HAVE_DEBUG_CAR is not set +# CONFIG_DEBUG_PIRQ is not set +# CONFIG_HAVE_DEBUG_SMBUS is not set +# CONFIG_DEBUG_SMI is not set +# CONFIG_DEBUG_SMM_RELOCATION is not set +# CONFIG_DEBUG_MALLOC is not set +# CONFIG_DEBUG_ACPI is not set +# CONFIG_REALMODE_DEBUG is not set +# CONFIG_TRACE is not set +# CONFIG_ENABLE_APIC_EXT_ID is not set +CONFIG_WARNINGS_ARE_ERRORS=y +# CONFIG_POWER_BUTTON_DEFAULT_ENABLE is not set +# CONFIG_POWER_BUTTON_DEFAULT_DISABLE is not set +# CONFIG_POWER_BUTTON_FORCE_ENABLE is not set +# CONFIG_POWER_BUTTON_FORCE_DISABLE is not set +# CONFIG_POWER_BUTTON_IS_OPTIONAL is not set +CONFIG_REG_SCRIPT=y +CONFIG_MAX_REBOOT_CNT=3 diff --git a/docs/future/dumps/grub.cfg b/docs/future/dumps/grub.cfg @@ -0,0 +1,38 @@ +set default="0" +set timeout=1 +set pager=1 + +menuentry 'Trisquel GNU/Linux with linux-libre 3.14.4' { + linux (ahci0,1)/boot/vmlinuz-3.14.4-gnuowen root=/dev/sda1 processor.max_cstate=2 drm.debug=0x06 console=tty0 console=ttyS0,115200n8 + initrd (ahci0,1)/boot/initrd.img-3.14.4-gnuowen +} +menuentry 'Parse ISOLINUX menu (USB)' { + set root='usb0' + syslinux_configfile -i (usb0)/isolinux/isolinux.cfg +} +menuentry 'Parse ISOLINUX menu (CD)' { + set root='ata0' + syslinux_configfile -i (ata0)/isolinux/isolinux.cfg +} +menuentry 'Scan for GRUB configurations on the internal HDD (Permits to load other OS or distributions)' { + insmod regexp + insmod ahci + insmod part_msdos + for x in (ahci0,*) ; do + if [ -f "$x/grub/grub.cfg" ] ; then + submenu "Load Config from $x" $x { + root=$2 + source /grub/grub.cfg + unset superusers + } + fi + if [ -f "$x/boot/grub/grub.cfg" ] ; then + submenu "Load Config from $x" $x { + root=$2 + source /boot/grub/grub.cfg + unset superusers + } + fi + done +} + diff --git a/docs/future/dumps/grub_memdisk_serial.cfg b/docs/future/dumps/grub_memdisk_serial.cfg @@ -0,0 +1,10 @@ +#Serial and keyboard configuration, very important. +serial --speed=115200 --unit=0 --word=8 --parity=no --stop=1 +terminal_input --append serial +terminal_output --append serial +terminal_input --append at_keyboard #add keyboard support. + +set prefix=(memdisk)/boot/grub + +set root='cbfsdisk' +source (cbfsdisk)/grub.cfg diff --git a/docs/future/dumps/kernel312_irc b/docs/future/dumps/kernel312_irc @@ -0,0 +1,1590 @@ +<hr/> + + <h1 id="todo_cb5926_paulmenzel">Coreboot 5926 test for Paul Menzel</h1> + <p> + Coreboot log when running Video BIOS (grub payload) and <a href="http://review.coreboot.org/5926">http://review.coreboot.org/5926</a>. + </p> + <p> + Result (ThinkPad X60): <a href="dumps/coreboot_5296_oprom_grub_cbmemc">cbmem -c output</a><br/> + Config used on the X60 (grub payload and vbios): <a href="dumps/coreboot_5926_oprom_grub_config">.config</a> + </p> + + + + + + + + + + + + <h1 id="todo_cb5893_paulmenzel">Coreboot 5893 test for Paul Menzel</h1> + <p> + <a href="dumps/x60_5893_vbios.tar.gz">With VBIOS</a><br/> + <a href="dumps/x60_5893_native.tar.gz">With native graphics</a> (replay code). + </p> + <p> + Here is a crash dump from running native graphics (): <a href="dumps/x60_5893_native_crashdump">/sys/class/drm/card0/error</a>. + </p> + +<hr/> + +<h1 id="i945_stolenmem_fix">early attempt: i945 stolen memory fix (for kernel 3.12/later) (this attempt failed)</h1> +<p> +Back then we had no idea that GTT address was incorrect, and we had no idea what was causing the issue. + +<pre> +Note: see <a href="#i945_312fix">this fix</a> for the initial fix that was found. + +<b><font color="red">not working yet</font></b> +<a href="http://review.coreboot.org/#/c/5885/" >http://review.coreboot.org/#/c/5885/</a> + +untested. will test this. +checkout 5320. cherry pick 5345 on top. +mannually apply changes from 5884/1 and 5885/3 +make backlight changes as in #x60_native_notes and #t60_native_notes +test this on X60 and T60. + +If it works, manually apply 5885 to 5320 alone and then push with 5320 as dependency. +Rebase that new change ID, and rebase 5345 (pushing it as new change ID). +Manually merge the rebased 5345 into the new patch, and then push that. + +Boot with grub (obviosly!) and kernel 3.14.4 as before (with 17fec8a left untouched!). + +Note: tidy these notes! (so others can follow) + +get those logs: +Make a copy of these files: + * /var/log/dmesg + * /var/log/kern.log + * /var/log/Xorg.0.log + * /var/log/Xorg.0.log.old (If you have to restart gdm) + * /proc/ioports + * /proc/iomem +Record these outputs: + * sudo intel_reg_dumper + * uname -r + * lspci -vvnn +Do this first: <b>$ sudo modprobe msr</b> (then do as below): + * sudo inteltool -a --> in coreboot/src/util/inteltool +Make a copy of: + * coreboot serial output log. + --> Get it from serial port, or get it like that: + --> <b>./cbmem -c</b> (under coreboot/util/cbmem) +Output from source tree: +$ git log -p | head -150 (localhost/x60gitlog) +$ git diff (localhost/x60gitdiff) +Make a copy of the .config from coreboot source tree + ^ (localhost/x60config) +3D acceleration test (test if 3.12+/stolenmem issue is fixed): + - Run openarena (1024x768 res), say if it works. (note: Press tilde, do <b>/cg_drawfps 1</b>) + - Run tuxcart (1024x768 res), say if it works. + - Run neverball (1024x768 res), say if it works. + - Run glxgears, report what you see. + +Some results on the X60 (3D still doesn't work, openarena and tuxkart were slow): +<a href="dumps/5885_logs.tar.gz">5885_logs.tar.gz</a> +git diff: http://paste.debian.net/102618/ + +In src/northbridge/intel/i945/raminit.c +PaulePanter: vimuser: In your next step could you please add +PaulePanter: printk(BIOS_DEBUG, "BSM = 0x%08x\n", pci_read_config32(PCI_DEV(0,2,0), BSM)); +PaulePanter: before +PaulePanter: pci_write_config32(PCI_DEV(0,2,0), BSM, (tolud * MiB - 64 * MiB) & 0xfff00000); +done +Also removing the #if statement around those 2 lines above. +Also adding it after that line aswell, per advice from PaulePanter + +Some new results on the X60 after doing the above (3D still doesn't work, openarena and tuxkart were slow): +<a href="dumps/5885_logs_2.tar.gz">5885_logs_2.tar.gz</a> + +PaulePanter: vimuser: No idea if you can write with `devmem2`. Never used it. +PaulePanter: vimuser: It would indeed be interesting to know what value the BSM has with the vendor BIOS. +Note to self: do that. + +PaulePanter said: I have `& 0xfff00000` and phcoder uses `& 0xfffff000`, so it looks like I have the ordering incorrect. + + +Look at that discussion: +http://lists.freedesktop.org/archives/intel-gfx/2014-May/046309.html +http://lists.freedesktop.org/archives/intel-gfx/2014-May/046310.html +--> if BSM register is read-only, then is there something els ethat we might have missed? + +</pre> +</p> + + + + + + + + + + + <h2><a name="kernel312bugs">kernel 3.12+ bugs (X60/T60 native init)</a><a href="#pagetop">Back to top of page</a></h2> + <p> + Some further notes to refer to later (WARNING: long! These are collected IRC logs for later reference. Most of the + logs are not useful or relevant, and will be deleted later): + +<pre> +Note: see <a href="#i945_312fix">this fix</a> for the initial fix that was found. + +see: <a href="http://www.coreboot.org/Board:lenovo/x60#Problems_in_native_graphics_code_exposed_by_recent_kernels" >http://www.coreboot.org/Board:lenovo/x60#Problems_in_native_graphics_code_exposed_by_recent_kernels</a> +see: <a href="http://www.coreboot.org/Lenovo_x60x_vgainit_todos" >http://www.coreboot.org/Lenovo_x60x_vgainit_todos</a> + +Non-coreboot (not even i945) platforms also have issues with 3.12+ +see: <a href="https://bugs.freedesktop.org/show_bug.cgi?id=76520" >https://bugs.freedesktop.org/show_bug.cgi?id=76520</a> + +Is this relevant?: <a href="http://lists.freedesktop.org/archives/intel-gfx/2014-February/040771.html" >http://lists.freedesktop.org/archives/intel-gfx/2014-February/040771.html</a> + + + +note: read below. +and note: on later kernels they also can't seem to init the GPU properly without vbios or native gfx, whereas older kernels could. + +PaulePanter: damo22: There is also a Linux and coreboot native graphics incompatibility documented in the Wiki (by samnob). +PaulePanter: http://www.coreboot.org/Board:lenovo/x60#Problems_in_native_graphics_code_exposed_by_recent_kernels +vimuser: PaulePanter, that only exists with kernel 3.12 and above. +PaulePanter: vimuser: Do you have time to report it to the Freedesktop Bugzilla? +funfunctor: patrickg: I think its related to recent changes we had done to toolchain.in +vimuser: Yes. What info do you need ? +PaulePanter: vimuser: It’s a regressions and these are normally not allowed with Linux’ no regression policy. +vimuser: What do you think would happen then, after I made that report? +PaulePanter: vimuser: https://01.org/linuxgraphics/documentation/how-report-bugs +vimuser: You can look at it 2 ways: kernel broke, or kernel fixed a bug which broke coreboot. +PaulePanter: vimuser: Hopefully they’ll fix it. +vimuser: so: either coreboot is broken, or kernel is broken. +vimuser: PaulePanter, kernel 3.12+ should work just fine on lenovo bios, so my opinion is that the native gfx in coreboot is what's buggy. +PaulePanter: vimuser: You can also check with the developers in #intel-gfx. But first report the bug so you can reference it. +vimuser: Do you think I should just copy what's in the coreboot wiki already? +PaulePanter: vimuser: Does not matter. If it worked before 3.12, it should work afterward. +vimuser: It seems pretty complete (as far as reporting it is concerned). +vimuser: PaulePanter, my basic point is that I'm on the fence as to whether this is linux's problem, coreboot's problem, or both. +PaulePanter: vimuser: That would probably help. If they need other information, the Intel folks will ask you for it. Daniel Vetter and the other Intel folks are very responsive in my experience. +vimuser: So you think then that there would be a patch specifically for i915 + coreboot_native_init +PaulePanter: vimuser: I do not know. They hopefully figure it out. +vimuser: PaulePanter, I will do it. +PaulePanter: vimuser: And as I wrote, it is a regression. As far as I understood it, even if the firmware/hardware is broken, Linux should not introduce regressions. +vimuser: PaulePanter: at the very least, it might offer a new perspective. this whole issue has been very one-sided so far: it has only been coreboot community that talks about it. It has probably gone unobserved in kernel/intel community. +vimuser: The intel/kernel people might even be able to (easily) spot a fix for coreboot. +vimuser: I hadn't even considered this possibility before, I thought it was only a coreboot problem. Talking to those other people definitely makes sense. + +PaulePanter of #coreboot made the initial report to Freedesktop tracker: + +PaulePanter: vimuser: Hi. Did you report the Linux regression to the Freedesktop bug tracker? +PaulePanter: vimuser: Understood. Do you have an account for the Freedesktop bug tracker? +vimuser: PaulePanter: I do not have an account for Freedesktop bug tracker, but I think I could get one? +PaulePanter: vimuser: Yes, it is easy to register. +vimuser: PaulePanter, there's reporting and there's reporting properly; I want to compile my report first, before I make it. +PaulePanter: vimuser: As you do not know what they need, I think it is the wrong approach. +vimuser: Since the people that I am reporting to will be unfamiliar with the issue, and might not even know about coreboot, or only vaguely know. +PaulePanter: vimuser: I’ll report the issue and give you the URL. You can then add to it. +vimuser: PaulePanter: Good point. I can make it brief describing it as best I can, and then I can answer any specific questions. +vimuser: PaulePanter, you can use my notes at http://libreboot.org/howto.html#kernel312bugs if you like, it's a collection of insights plus links to those pages on the coreboot wiki that talk about the issue. +vimuser: (in case there is anything in the notes that might be helpful) +vimuser: PaulePanter, are the intel i915 devs of freedesktop also the ones working on the i915 code in kernel.org? (I'm slightly confused about this) + +THE REPORT: + +PaulePanter: vimuser: The Wiki talks about crashes. +PaulePanter: vimuser: https://bugs.freedesktop.org/show_bug.cgi?id=79038 + +PaulePanter: vimuser: The Wiki talks about crashes. +PaulePanter: vimuser: https://bugs.freedesktop.org/show_bug.cgi?id=79038 +vimuser: PaulePanter, thanks. I'll add to it and help any way I can. +PaulePanter: vimuser: Add `drm.debug=0x06` to the Linux command line (probably configuring in GRUB) and please add `/var/log/dmesg` to the bug report. (Or the output of `dmesg`.) +PaulePanter: vimuser: They also need `/var/log/Xorg.0.log` and your distribution and exact Linux kernel version `uname -r`. +vimuser: PaulePanter: there are basically 2 versions of native init: 3998 (based on replay, only works on X60 with XGA screen - also what libreboot currently uses) and 5320 (much better, works on more screens, 5345 can use it to enable T60 - not yet in libreboot) +vimuser: PaulePanter: should I do this test on both versions? (libreboot and coreboot+5320+5345) + +vimuser: PaulePanter: should I do this test on both versions? (libreboot and coreboot+5320+5345) +vimuser: PaulePanter: nonetheless, I will do both, and make that report for you now. +vimuser: Do I do this on pre-3.12 kernel or 3.12+ ? +PaulePanter: vimuser: I’d say Linux 3.12+. +PaulePanter: vimuser: Do you know which coreboot patches samnob used? + +vimuser: PaulePanter: very well. http://jxself.org/linux-libre has latest kernels +vimuser: I will install that. +vimuser: I do not know what coreboot patches samnob used. Probably 3998 (this was a long time ago). +vimuser: Definitely change ID 3998 (review.coreboot.org gerrit): http://review.coreboot.org/#/c/3998/ + + +vimuser: PaulePanter: here is the information that you requested: http://libreboot.org/logs/3998_Xorg.0.log http://libreboot.org/logs/3998_dmesg http://libreboot.org/logs/3998_uname +vimuser: PaulePanter: that bug in the report doesn't happen with the above -- it's an older kernel. +vimuser: Do they want me to try 3.12+ instead? +vimuser: PaulePanter: you should also give them these links to the lastest code for native graphics: +vimuser: http://review.coreboot.org/#/c/5320/ + +PaulePanter: vimuser: Thank you for getting the logs. Please register and upload the files yourself. +vimuser: Yes, ok. I will also get the same logs again for a kernel that is broken (3.12+) +vimuser: I will repeat both processes again for coreboot+5320+5345, as currently I am getting these on libreboot. +vimuser: More logs can't hurt, the worst that can happen is they will ignore the ones they don't need. I want to make sure they have everything they need. + +samnob: vimuser: samnoble.org/thinkpad/kernel/linux-image-3.14.4-gnuowen_1_i386.deb and http://samnoble.org/thinkpad/kernel/linux-image-3.14.4-gnu-stolenmem-owen_1_i386.deb latest linux-libre without and with 17fec8a reverted. +PaulePanter: vimuser: Thanks. + +vimuser: samnob, thanks. +vimuser: but we are trying to get kernel 3.12+ to work without users having to patch it +vimuser: either by fixing coreboot, or patching around coreboot in the kernel +vimuser: eventually both +samnob: Yes, just providing you kernels for the bug. +vimuser: ah right. +vimuser: with and without. that is useful. i was going to use jxself kernels. that is useful. +vimuser: I'll use yours then ;) +vimuser: dpkg -i ? + +samnob: Though based on the devs comment in the bug I think you're hope of the driver working around it is unlikely. +vimuser: can't hurt to try +samnob: dpkg -i will work fine. +samnob: (though gdebi is more fun.) +samnob: there's a version symlink_hook in that same folder that is handy for grub2 payload users too. +vimuser: samnob we think it might be classed under linux "no regression" policy +vimuser: PaulePanter's idea +samnob: can't hurt to try :) + +Here is the debugging results then: <a href="coreboot_native_3.12_bug.tar.gz" >coreboot_native_3.12_bug.tar.gz</a> + +--- + +http://undeadly.org/cgi?action=article&sid=20131120060004 was suggested +(also refer back te the datasheet) + +---- + +I have since been alerted to this bug report, which is unrelated to us +but shows that 3.12 also breaks later systems on Lenovo BIOS (as far as I can tell): + +https://bugzilla.kernel.org/show_bug.cgi?id=71391 + +-- + +PaulePanter: vimuser: If you run the Lenovo X60 right now, could you just paste it now. It should not change between all your tests. +PaulePanter: vimuser: It would really be helpful to have it now. +vimuser: My workstation X60 is running coreboot+5320 (and modification for backlight control support) +vimuser: Shall I take iomem output from that? +vimuser: kernel 3.2 is in use +PaulePanter: vimuser: Yes. Please. +vimuser: For you record: +vimuser: $ uname -r +vimuser: 3.2.0-56-generic-pae +vimuser: distro: trisquel 6 +vimuser: PaulePanter: http://paste.debian.net/101404/ + +PaulePanter linked to this: +http://www.intel.com/content/dam/www/public/us/en/documents/datasheets/3rd-gen-core-desktop-vol-2-datasheet.pdf +--------------- + +PaulePanter: patrickg: As the resident i945 export, do you know where the register GBSM (Graphics Base of Stolen Memory) should be set? +PaulePanter: patrickg: Is the VGA Option ROM responsible for that? +PaulePanter: damo22: You do not see any problems with the VGA Option ROM, right? +damo22: PaulePanter: i am running vga rom with updated kernel (after the patch) and experience no problems with video +PaulePanter: damo22: Thank you for the confirmation. +PaulePanter: src/northbridge/intel/i945/northbridge.c: printk(BIOS_SPEW, "Base of stolen memory: 0x%08x\n", +patrickg: PaulePanter: what's that, 0x5c? +patrickg: h, no +PaulePanter: + /* Almost universally we can find the Graphics Base of Stolen Memory +PaulePanter: + * at offset 0x5c in the igfx configuration space. On a few (desktop)patrickg: PaulePanter: I think we never configured that but left it to vgabios +patrickg: PaulePanter: we only configured the RAM side +PaulePanter: patrickg: Thanks. So with native VGA init, coreboot needs to do that too. +<b><font color="red">damo22: we just need to write the gfxstolen base to gma config space at 0x5c</font></b> +damo22: that should fix it +damo22: because then the kernel will try to read that +damo22: hmm but if the generation of the gma is not >=3 it will assume it is above top of memory +patrickg: well, it is +damo22: patrickg: do you happen to know if the x60 gma is generation 2 or 3? how do i find out +PaulePanter: damo22: lspci ? +damo22: (rev 0x)? +PaulePanter: lspci -nn +damo22: never mind i will ctags the kernel tree +patrickg: but bbl +patrickg: damo22: code.metager.de applies openGrok on tons of open source projects. probably to linux, too +damo22: thanks patrickg +damo22: okay, i945g/gm is generation 3 +damo22: its nothing to do with the lscpi revision +PaulePanter: damo22: How did you check that? +PaulePanter: … it is 3rd gen? +damo22: PaulePanter: its in the i915_drv.c in the kernel +damo22: eg, i965g/gm is generation 4 +PaulePanter: Ok. +damo22: its also NOT valleyview +* pl4nkton is now known as pl4nkton`away +PaulePanter: damo22: ? +PaulePanter: Who said that? +damo22: im trying to figure out which path the kernel takes before and after the patch +damo22: it must be different +PaulePanter: damo22: https://bugs.freedesktop.org/show_bug.cgi?id=79038#c12 +PaulePanter: damo22: Before they calculate it manually and afterward they read out that register, which the firmware should program, right? +PaulePanter: src/northbridge/intel/i945/i945.h:#define TOLUD 0x9c /* Top of Low Used Memory */ +PaulePanter: Off topic, how do I make Vim and Ctags jump to the correct header definition. If I Ctrl + click on `TOLUD` in `src/northbridge/intel/i945/raminit.c` it jumps into the header of `intel/fsp_sandybridge/northbridge.h` instead of `src/northbridge/intel/i945/i945.h`. +PaulePanter: ? +damo22: i have the same problem, there is a way to configure it to pop up a list of matches so you can select the right one but i dont know how +PaulePanter: damo22: Ok. Good to know I am not the only one. +<b><font color="red"> +damo22: okay, so for gen 3 i915, (i945/m) we can do what i said above and it should work +PaulePanter: Is “graphics datastolen memory size (PCI Device 0 offset 52 bits 7:4)” configurable and programmed by the firmware or is it fixed if the IGP is enabled and can just be read? +PaulePanter: damo22: Yes. +damo22: its just a matter of setting the base address in the register +damo22: i think the only difference is that in the kernel it is assumed that it is aligned to 0x100000 +damo22: kernel does this: base &= ~((1<<20) - 1); +damo22: but coreboot does this: pci_read_config32(dev, 0x5c) & ~0xf, +damo22: possibly a one liner +damo22: change ~0xf to ~0xfffff lol +samnob: vimuser: samnoble.org/thinkpad/kernel/linux-image-3.14.4-gnu-stolenmem-owen_2_i386.deb and linux-image-3.14.4-gnuowen_2_i386.deb with CONFIG_STRICT_DEVMEM unset. No PAE as always. +samnob: damo22: thanks for looking into this. +</font></b> +vimuser: damo22: you are the most awesome person ever. I'm stilll preparing my dev/debugging environment and you speculate this already. I will try it soon. +vimuser: samnob: thank you for confirming. +vimuser: samnob: ok, /dev/mem support and non-PAE. excellent! +samnob: vimuser: don't overlook that revision 2 those, are new debs with STRICT_DEVMEM unset +damo22: vimuser: its much quicker to read and compare code than to compile kernels and flash firmware +PaulePanter: vimuser: I think your testing is not needed until you get a patch. +PaulePanter: damo22: TOLUD (PCI Device 0 offset BCh bits 31:20) +vimuser: PaulePanter ? +vimuser: Yes I understand that. I was about to debug, but now we will test damo22's advice first. +damo22: PaulePanter: i think intel_gma_init is being called with unaligned physical address for graphics mem + +PaulePanter: vimuser: BDSM—Base Data of Stolen Memory Register +PaulePanter: http://www.intel.com/content/dam/www/public/us/en/documents/datasheets/3rd-gen-core-desktop-vol-2-datasheet.pdf + +PaulePanter: vimuser: The methods you try just read it out and never set it. +PaulePanter: This register contains the base address of graphics data stolen DRAM memory. BIOS determines the base of graphics data stolen memory by subtracting the graphics data stolen memory size (PCI Device 0 offset 52 bits 7:4) from TOLUD (PCI Device 0 offset BCh bits 31:20). +damo22: PaulePanter: im pretty sure BDSM is only present in core iX cpus +vimuser: PaulePanter, yes my method was to go about to be sure where it is set, and then try to set it properly in 5320. +PaulePanter: vimuser: The problem is already present with native graphics in coreboot master, isn’t it? +vimuser: damo22 took a shorter method to get the same result (hopefully. like you, i wait for him to confirm or deny success) +vimuser: PaulePanter, yes the 3.12+ glitches exist in 5320 changeset aswell as 3998 (the old replay version, which 5320 is a re-write of) +PaulePanter: vimuser: Sorry, I claim your tests would have never gotten any solution for the problem. +* martinr (~martin@8.36.227.227) has joined #coreboot +vimuser: PaulePanter, that is quite possible, but it was a test anyway. +PaulePanter: damo22: Chris Wilson and the Linux commit say that the BDSM is present, don’t they? +PaulePanter: + if (INTEL_INFO(dev)->gen >= 3) { +PaulePanter: + /* Read Graphics Base of Stolen Memory directly */ +vimuser: I actually did find where the stolen memory address was set, in /var/log/kern.log after using drm.debug=0x06 in those previous results i uploaded to freedesktop.org, but that was on coreboot/5320 with the address set incorrectly. +vimuser: just search for the word "stolen" in the log and you'll find it on one of the lines. + +PaulePanter: vimuser: It’s not *set* it is *read* in there. +vimuser: Oh right. +vimuser: But I thought when reading it, it has to know the address. So the address I saw must have been what was set? +vimuser: What am I missing? +damo22: okay so there is something to clarify, i915 driver is the same for all intel gpus even some that are physically located in cpu + +PaulePanter: vimuser: As it is not explicitely set beforehand it contains some incorrect value, which is then read. +PaulePanter: vimuser: That is the whole problem. +vimuser: I see. +vimuser: So, +vimuser: my tests would have been useless, then. + +<b><font color="red">damo22: it didnt work</font></b> +(note: can still try to make other changes: see testing notes below) + +damo22: oh wait, X just didnt detect the LVDS +damo22: in fact nothing did +damo22: but there were no errors +damo22: ok so when i plug external monitor X freezes and gives errors +damo22: and internal display isnt active +damo22: wierd, when i rebooted i got vga fine +damo22: i think linux kernel i915 is trying to do something with vgarom because it says "invalid rom contents" as first boot line +damo22: no i need to find out if the kernel is doing something bad without rom present +damo22: and then figure out how to enable lvds, because vga is working +vimuser: drivers/pci/rom.c: dev_err(&pdev->dev, "Invalid ROM contents\n"); +vimuser: in that: size_t pci_get_rom_size(struct pci_dev *pdev, void __iomem *rom, size_t size) +vimuser: /* Standard PCI ROMs start out with these bytes 55 AA */ +vimuser: if (readb(image) != 0x55) { +vimuser: dev_err(&pdev->dev, "Invalid ROM contents\n"); +vimuser: break; +vimuser: } +damo22: i guess i should focus on the fact that coreboot did not initialise the gfx at grub screen +damo22: i mean seabios +damo22: its difficult because linux does some reinitialisation of gfx +damo22: i thought i had this one in the bag +CareBear\: damo22 : it does complete reinit +damo22: i flicked throught the kernel i915 driver and it looks like it reads VBT tables from romheaders or something +damo22: if we are using native gfx init, those are not present right? +samnob: damo22: I think you need to be using grub2 to test native gfx init, seabios needs at least a stub of a vgarom. +CareBear\: damo22 : correct +CareBear\: samnob damo22 : if you want to use SeaBIOS you can use the SeaVGABIOS which will pick up a native framebuffer initialized by coreboot +damo22: does SeaVGABIOS install VBT stuff in the vgarom area? +CareBear\: damo22 : probably not the kind the framebuffer driver looks for +damo22: then it will fail with linux +CareBear\: damo22 : yes +damo22: CareBear\: can we write a vgabios stub that passes the signature tests and also has native VBT tables, but executes nothing? +damo22: otherwise we need to patch the linux kernel to ignore certain models that have no vgabios +CareBear\: damo22 : let's first find out what information is used in those tables +damo22: i have the code in front of me +damo22: drivers/gpu/drm/i915/intel_bios.c (kernel) +damo22: vimuser: no, i am trawling through linux driver code +vimuser: damo22: are you aware that certain kernels can initialize the GPU on X60 without the native gfx or oprom? (you don't see payloads, but kernel/X11 shows display +damo22: i have a feeling the linux kernel currently tries to load the vgarom regardless of PCH existance + +damo22: i think there are two problems with native gfx init, one problem is that the lvds isnt coming up (coreboot issue), the other is is with the linux kernel i915 driver that tries to read the vgarom that isnt there + +vimuser: damo22, what hardware are you testing your changes on? +vimuser: Did you try 5320 without your changes? +vimuser: (hardware: X60 or T60) + +Peter on 5320 talks about vga pipe not being enabled: this means that payload doesn't appear +on vga (only on lvds). OS can output on vga or lvds. so we need to get 5320 to output (during payload) on vga + +damo22: i just slept on it, and i think i know what the problem is + + * LVDS discovery: + * 1) check for EDID on DDC + * 2) check for VBT data + * 3) check to see if LVDS is already on + * if none of the above, no panel + + +1) it cant find the EDID because the i2c is failing to read with NAK +2) there is no VBT data because there is no vga option rom +3) coreboot is still not doing native init properly so the panel is still off + +Therefore linux assumes there is no LVDS. + +damo22: how do i enable cbmem console? i enabled it in menuconfig, do i need cbmem dynamically growing? +damo22: [*] Send console output to a CBMEM buffer\ +damo22: but i got nothing + +Guest-FR: Hi +Guest-FR: would you please check +Guest-FR: src/northbridge/intel/i945/gma.c +Guest-FR: function gma_func0_disable +Guest-FR: pci_write_config16(dev, GCFC, 0xa00) , sound wrong isn't it? + +damo22: Guest-FR: what do you think is wrong about it? +Guest-FR: per the datasheet (intel, so probably it is also wrong!) , the value should be "0x1b" +Guest-FR: page 74 +damo22: Guest-FR: can you link me to the datasheet +Guest-FR: damo22: congig16 is expecting 0x && 4 digits isn't it? +Guest-FR: damo22: e.i.: 0x1234 +damo22: Guest-FR: 0xa00 === 0x0a00 +damo22: same thing +Guest-FR: ok + +Guest-FR: here is the link for tha datasheet http://www.intel.com/Assets/PDF/datasheet/307502.pdf + +damo22: ty +damo22: Guest-FR: i am also working on this gma +damo22: Guest-FR: i am trying to figure out why native gfx init is not working on my X60 tablet + +Guest-FR: per gma.h, GCFC is 0xf0 /* Graphics Clock Frequency & Gating Control */ +damo22: Guest-FR: GCFC is missing from the datasheet +damo22: so how do you know its wrong +Guest-FR: it is my mistake.... I'm expecting to see 4 digits for conf16 +damo22: Guest-FR: ok, i would have expected GCFC to be on page 62 at the bottom but its missing +Guest-FR: probably we should make a dump to see the value we have with an original bios. what you think ? is it possible? +damo22: Guest-FR: however, GGC is mismatching between that datasheet and in coreboot gma +Guest-FR: intel is a fu*** company +damo22: ahh no, i looked up the wrong file +damo22: it matches +damo22: Guest-FR: i am assuming you are using patched gma to test? +Guest-FR: damo22: no, I use the original one +damo22: Guest-FR: http://review.coreboot.org/#/c/5320/ +Guest-FR: I try to port my board to coorboot https://github.com/coreboot-for-945g-m4/945g-m4 +Guest-FR: thx damo22 +damo22: Guest-FR: you need extra config in devicetree.cb with that +Guest-FR: damo22: http://review.coreboot.org/#/c/5762/ +damo22: Guest-FR: i cant view it +Guest-FR: oops, it is draft +Guest-FR: may I add you as a reviewer ? +damo22: Guest-FR: sure +Guest-FR: damo at zamodio? +damo22: correct +Guest-FR: done +Guest-FR: please feel free put comments (and be verbos, I'm not a developper :p ) +Guest-FR: probably my devicetree is not good, +damo22: it still wont load +Guest-FR: damien at zamaudio.com ? +damo22: yes +damo22: ok better +Guest-FR: probably you got an email ? +Guest-FR: for a review +damo22: Guest-FR: i dont see native gfx init +damo22: are you using vgarom? +Guest-FR: I'm using a PCIE card (Radeon X300) +damo22: dont you want to try to initialise the onboard gfx? +Guest-FR: why not, I'll give it a go :) +damo22: you showed me a whole bunch of code, but what is the problem? +Guest-FR: the serial is working, but it hang on "setting up static southbridge register ..." +Guest-FR: and some times, it went to "setting up Root Complex Topology" +damo22: Guest-FR: well, look for that message in the code and find the next message that should be displayed and you know the problem is between the two messaged +Guest-FR: there is some thing unstable +damo22: messages* +Guest-FR: ok +damo22: Guest-FR: if its too hard to find, add some printk's +damo22: i could really use a tip on how to enable cbmem console +damo22: im running blind + +Guest-FR: the msg ih at " src/northbridge/intel/i945/early_init.c " i945_setup_bars function +Guest-FR: so my problem is between "Setting up static southbridge registers..." and "Done" :) + +damo22: cat .config|grep CBMEM ===> http://paste.debian.net/101541/ why do i still not have any cbmem console? "No console found in coreboot table." +content of debian paste: +CONFIG_EARLY_CBMEM_INIT=y +# CONFIG_DYNAMIC_CBMEM is not set +CONFIG_CONSOLE_CBMEM=y +CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 +damo22: No coreboot CBMEM area found! +* Guest-FR (d5f5ab0b@gateway/web/freenode/ip.213.245.171.11) has joined #coreboot +Guest-FR: I'd like to understand: is there any difference betweent: pci_write_config16(LPC_DEV, 0x84, 0x0a01); + pci_write_config16(LPC_DEV, 0x86, 0x00fc); vs pci_write_config32(LPC_DEV, 0x84, 0x00fc0a01); +Guest-FR: for exemple: lenovo/x60/romstage.c we have: pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x84, 0x1601); however in the ich7 datasheet page 364 it is a conf32 + +phcoder-screen: damo22: for C segment. boot with oprom, then dd if=/dev/mem bs=64k of=seg_cdef.bin skip=12 count=4 +damo22: ok +damo22: is that the VBT table? +phcoder-screen: part of it is +damo22: phcoder-screen: http://www.zamaudio.com/mbox2/seg_cdef.bin +damo22: it looks correct because it mentions calistoga +damo22: phcoder-screen: as a general solution, would it be possible to write a script that takes a vgarom as input and outputs a vgarom stub that will have no executable code but still have the VBT stuff and signatures to fool the OS that real vgarom is there, and will detect panels etc +damo22: or is there a better way? + +phcoder-screen: damo22: there is a better way: generate it in coreboot. I have a tool to partially parse the roms. Trying it with yours. +damo22: cool + +phcoder-screen: damo22: http://pastebin.com/GsYhSaNB +Content of that paste: +signature: <$VBT CALISTOGA > +version: 1.00 +VBT size: 0xea0 +VBT checksum: 0x0 +BDB version: 1.29 +section type 254, size 0xea + type: 0 + relstage: 64 + chipset: 1 + LVDS + No TV + rsvd3[0]: 0x8 + rsvd3[1]: 0x3 + rsvd3[2]: 0x31 + rsvd3[3]: 0x33 + Signon: 13Intel(r)Calistoga PCI Accelerated SVGA BIOS +Build Number: 1313d.dal PC 14.20 Dev 10/17/2006 0:22:30 +DECOMPILATION OR DISASSEMBLY PROHIBITED + + Copyright: + Code segment: a + DOS Boot mode: 0 + Bandwidth percent: c0 + rsvd4: 0x3 + Bandwidth percent: 8 + rsvd5: 0x4 +section type 1, size 0x5 +General features: + panel_fitting = 0x3 + flexaim = 0x1 + download_ext_vbt = 0x1 + *enable_ssc = 0x1 + *ssc_freq = 0x1 + *display_clock_mode = 0x0 + disable_smooth_vision = 0x0 + *fdi_rx_polarity_inverted = 0x0 + legacy_monitor_detect = 0x1 + *int_crt_support = 0x1 + *int_tv_support = 0x0 +section type 254, size 0x20 +section type 2, size 0xcb + *CRT DDC GMBUS pin: 2 + DPMS ACPI: 0 + Skip boot CRT detect: 0 + DPMS aim: 1 + boot_display: { 0, 0 } + 6 devices + *device type: 1009 (TV) + *dvo_port: 5 + *i2c_pin: 0 + *slave_addr: 0 + *ddc_pin: 0 + *dvo_wiring: 0 + edid_ptr: 0 + *device type: 1022 (flat panel) + *dvo_port: 4 + *i2c_pin: 0 + *slave_addr: 0 + *ddc_pin: 3 + *dvo_wiring: 0 + edid_ptr: 0 + *device type: 0 (Empty) + *device type: 0 (Empty) + *device type: 0 (Empty) + *device type: 0 (Empty) +section type 3, size 0x1 +section type 4, size 0x1c +section type 254, size 0x69 +section type 6, size 0x16d +section type 7, size 0x7 +section type 8, size 0x3d +section type 10, size 0xcb +section type 11, size 0xc7 +section type 12, size 0xf + *LVDS config: 1 + *Dual frequency: 1 +section type 13, size 0x3 +section type 14, size 0x9 +section type 15, size 0x8b +section type 16, size 0x84 +section type 17, size 0x8 +section type 18, size 0xc +section type 19, size 0x20 +section type 20, size 0x9e +section type 22, size 0x15 + *Panel type: 3 +section type 23, size 0x48 +section type 24, size 0x28 +section type 25, size 0x28 +section type 26, size 0x2 +section type 40, size 0x8 +section type 41, size 0x91 +section type 42, size 0x4a0 +section type 43, size 0x61 +section type 44, size 0x15 +damo22: phcoder-screen: does that mean for every supported board, an extra step will be needed to parse the roms so that the port can be done +damo22: *CRT DDC GMBUS pin: 2 +damo22: i think it is trying pin 3 +phcoder-screen: damo22: CRT is VGA +phcoder-screen: ddc_pin is 3 under lvds section +damo22: oh yeah +phcoder-screen: damo22: we already need some info in device tree to init. I think we can reuse it +phcoder-screen: I can upload my parser if you want +damo22: sure, i can parse my T60 and X60t +damo22: and eventually T61 +phcoder-screen: CL 5842 +damo22: thanks + +damo22: phcoder-screen: do you think the EDID is failing to read in linux because the VBT is missing? + +phcoder-screen: damo22: it's a likely explanation. I'd reput first 64k of your dump back to place +damo22: where does it belong in the flash? +damo22: c0000? +phcoder-screen: damo22: nowhere. c0000 is in RAM +damo22: so how do i ensure it gets loaded into ram at c0000 +phcoder-screen: damo22: memcpy +damo22: im convinced it will work if i do that +damo22: thats like loading the vgarom +damo22: but without executing it +phcoder-screen: damo22: yes +damo22: couldnt i just select it in menuconfig, but comment out the code that runs it? +phcoder-screen: yes +phcoder-screen: and keep in mind that oprom is self-modifying +damo22: yes so i need the final dump to load not the original +phcoder-screen: yes + + + +-- + +Side discussion (in #libreboot, not #coreboot as above): + +vimuser: damo22: what was the problem? +damo22: EDID is not being read in linux +damo22: well it is, but it fails +damo22: probably because the VBT signature is missing from the oprom +vimuser: oprom? +vimuser: You mean native init code? +vimuser: that it doesn't put the proper data in vbt +damo22: there is some special metadata in the oprom that native init doesnt put in +damo22: linux looks for it +damo22: thats how it knows where to read the EDID from +damo22: otherwise it uses a default address that could be wrong +damo22: in some cases it works +damo22: other cases like my X60t it fails +vimuser: that would explain why "read-edid" utility deosn't work on natisev gfx at the mament +vimuser: moment +vimuser: Basstard` ^ + +damo22: vimuser: phcoder wrote an experimental utility to parse some of the VBT tables from a vgarom +vimuser: Did he share it with you? +damo22: yes +vimuser: Did he upload it publicly? +damo22: http://review.coreboot.org/#/c/5842/ +vimuser: Ok cool. +vimuser: Do you think I should try it? + +damo22: you could use it to get more info from all your known boards, collect the parsed tables in a folder correctly named with the type of panel and the type of laptop +vimuser: So as per #coreboot, my understanding is: move to new stolen memory address, find that metadata and how it's calculated and write that (memcpy/write32) in native init, get VBT tables parsed from ROM, replicate that in native gfx (stub code, just the addresses and pointers to the native init code) +vimuser: Should this be run an a vgabios.bin, or on a system where vga bios is running (parse it in memory) ? +vimuser: or both? +damo22: we havent got a solution for native init yet, but we do need to collect info from different models +damo22: to see how they compare +vimuser: yes so, vgabios.bin (file) or running vga bios? +damo22: and also we can add it to devicetree.cb somehow later +damo22: preferably the running vgabios +vimuser: ok +damo22: you can dump it with this command: +damo22: sudo dd if=/dev/mem bs=64k of=runningvga.bin skip=12 count=1 + +damo22: coreboot/util/intelvbttool + +damo22: gcc intelvbttool.c -o intelvbttool + +vimuser: it would be good for you to run intelvbttool on vgabios.bin and runningvgabios.bin. (where vgabios.bin is extracted from lenovo rom, and runningvgabios.bin is dd'd from memory after it executed) +vimuser: right? +vimuser: (I will do the same) +vimuser: just runningvgabios.bin ? +damo22: its useless in the factory bios +damo22: for the purposes of this test +vimuser: ok +vimuser: Can't hurt though (might be useful later). +damo22: not really, it might be modified at runtime and we wont know anything about it +damo22: we need final values +damo22: the rest is irrelevant +vimuser: Yes. I was saying to run it on final dump, and factory dump. +vimuser: but ok, i will only do it for final dump + +-- + +further discussion, continued in #coreboot: + +damo22:we could generate fake_vbt arrays for each model +damo22:vimuser: whats the link to the vbt stuff again +vimuser: http://review.coreboot.org/#/c/5396 for X230 +damo22:vimuser: no on libreboot +vimuser: I also added this to the notes at http://libreboot.org/howto.html#i945_vbt and http://libreboot.org/howto.html#intelvbttool_results for future reference. +vimuser: on libreboot? I don't understand. +damo22:its possible that the VBT is modified by the vgarom depending on the panel it detects, assuming it can do that +damo22:only problem is, you need info from the VBT to know where to read the EDID, so how does the vgarom do it? +damo22:maybe its safe to assume that the EDID i2c will be the same for all panels +vimuser: Might be hardcoded (what CareBear calls "stupid magic numbers") +damo22:so we should check all VBTs of the same laptop model and verify that the EDID i2c or ddc pin is the same for all panel types +vimuser: Sorry, when you say VBT do you mean the runningvga.bin dump taken with dd when vgarom is running? +damo22:then we can hardcode that value into the coreboot devicetree.cb + +vimuser: I see. it's an i2c bus that connects lvds/vga/vga out +kmalkki:damo22: in your opinion, where is this EDID eeprom physically located? +damo22:kmalkki: on the panel, or the transformer for the panel +kmalkki:damo22: what do you think is a transformer for the panel? +damo22:some circuitry that interfaces between the lvds connector and the panel itself +damo22:on the T60 there is a separate module afaik +damo22:on other models it might be incorporated into the panel idk +damo22:kmalkki: i believe that the VBT has information regarding which pin of the i2c to read for the EDID eeprom/storage +damo22:and it varies panel to panel +kmalkki:would it surprise you DDC signals are often not on the panel connector +damo22:hmm + +kmalkki:like, x60 schematics is easily available, do check on some alternative ways how these are done +damo22:ok + +kmalkki:damo22: for t60 however... LCD connector does have EDID lines +damo22:kmalkki: well it would be nice to have a general solution to EDID reading +damo22:i need to understand the wiring more and the VBT +kmalkki:DDC signals originate from the graphics device +kmalkki:that will be Intel for some, ATI for some T60 ? + +damo22:kmalkki: linux expects the VBT to be in the vgarom memory area, because it uses it to identify when a panel exists, so coreboot should provide VBT like a vendor bios ? + +damo22:when vgarom is used with coreboot there is no problem , but for native gfx init it doesnt always work +kmalkki:ok.. so we can ignore ATI case for now +damo22:kmalkki: is that because no native init will be done for that case? +damo22:so the vgarom will always work +kmalkki:ok.. so do you know VBT format? +damo22:kmalkki: phcoder has done lots of work on it already +kmalkki:and.. is there a problem in reading the EDID? +damo22:kmalkki: idk yet, i need to test +damo22:im having trouble building a coreboot rom that uses coreboots native framebuffer so i can see if it worked +damo22:linux reinits the gfx so its not a good test +damo22:but in any case, without the VBT, linux cant reinit my gfx +damo22:it fails to read the EDID +damo22:and without a dock, and cbmem console isnt working, i cant get the coreboot log to check what actually happened +kmalkki:what do you mean cbmem console not working? +damo22:kmalkki: i enabled it in menuconfig and built a rom, but when i run it on my X60t cbmem -c reports No console found +kmalkki:we should get it fixed then +kmalkki:paste your .config +damo22:http://paste.debian.net/101644/ + +kmalkki:git hash is from local tree.. it does work on master, right? +damo22:idk +damo22:i just cherry picked some native gfx patches +damo22:why would it affect cbmem console +kmalkki:mess up MTRRs or memory space mapping or UMA region... +damo22:ok +kmalkki:are those patches on gerrit you picked? +damo22:well i need these patches because that is why i need the console +damo22:yes +damo22:actually i did minor changes too +damo22::S +kmalkki:yep.. which patches exactly +damo22:5320 +damo22:then i changed 2 lines +damo22:a minor devicetree.cb line and this: +damo22:- intel_gma_init(conf, pci_read_config32(dev, 0x5c) & ~0xf, +damo22:+ intel_gma_init(conf, pci_read_config32(dev, 0x5c) & ~0xfffff, +kmalkki:ok.. also paste 'git log' so I find common hash from master +damo22:http://paste.debian.net/101645/ + +damo22:does anyone have better google xen than me, i cant seem to find a pdf of x60 schematics +Basstard' damo22: Do you mean this? http://www.computerservice.es/wp-content/uploads/2013/05/IBM-X60.pdf + +damo22:yep thanks +kmalkki:and now that I am awake, I see DDC signals on x60 LCD too +kmalkki:just.. no DDC or I2C in the signal name but EDID +damo22:yeah +damo22:what bus does the lvds connector use +damo22:is that i2c? +damo22:or should i say, how standard is that lcd connector they are using on the X60 +kmalkki:mainboard side is completely non-standard AFAIK +damo22:ohhh +kmalkki:panel side has a few variants on the LVDS input +damo22:ok +damo22:this is not easy to generalise then +damo22:SPWG_EDID_CLK and SPWG_EDID_DATA are the signals i found on the connector + +kmalkki:yes. and it looks like phcoder-screen has done all the work to read the EDID +damo22:yes but the address and pins required are stored in the VBT i think +kmalkki:solve your CBMEM console, please +damo22:yea +Basstard' damo22: Here's a cleaner one: http://pdf.datasheetarchive.com/indexerfiles/Datasheets-USER/DSAUPLD00006054.pdf +kmalkki:just verify 1315730 works +damo22:1315730? + +GNUtoo-irssi: vimuser: hi, 0x58BF58BE works fine --- cool. (not related to these discussions, but GNUtoo is happy). + +<a name="gnutoo_gtt"></a> +GNUtoo-irssi: phcoder-screen: if you're still working on native GPU init for i945(it seems so), I've an observation: +GNUtoo-irssi: gtt is not setup correctly anymore with your versions, the kenrel complains +GNUtoo-irssi: it was with a replay version, so if you're still working on it it may be an usefull hint +GNUtoo-irssi: I've added the code that works inside git, so if you want/need it, ping me +phcoder-screen:damo22: yes +GNUtoo-irssi: beside the kernel warning, the effect is slow 3D with a 3.10 lts kernel +damo22:GNUtoo-irssi: can you push it as a notformerge? +GNUtoo-irssi: ok, good idea +GNUtoo-irssi: ah sigh, again... +GNUtoo-irssi: ! [remote rejected] HEAD -> refs/for/master/NOTFORMERGE-reference-i915_gpu_init-x60 (change 3992 closed) +GNUtoo-irssi: I'll change the IDs +damo22:GNUtoo-irssi: have you seen 5230? +damo22:5320* +phcoder-screen:damo22: rank 0 of either channel is configured but not rank 1 +GNUtoo-irssi: let me look +GNUtoo-irssi: I've tried some recent branch for the t60 +GNUtoo-irssi: it works well, beside the gtt init issue I just described +damo22:GNUtoo-irssi: given that you were working on 3992 which is closed are you able to rebase your changes on top of 5320? +damo22:hmm 3992 was merged +damo22:phcoder-screen: my dimms are dual rank +<stefanct> GNUtoo-irssi: i am not too familiar with gerrit, but that error message seems to indicate that you should not try to push 3992 again because it is already merged... rebasing the remains of your changes on top of that (or origin/master) should fix that *i guess* + +URL to topic: http://review.coreboot.org/#/q/status:open+project:coreboot+branch:master+topic:NOTFORMERGE-reference-i915_gpu_init-x60,n,z +(note: this is old code, not *directly* useful but might be useful later. put this somewhere else in howto.html later) + +GNUtoo-irssi: done, NOTFORMERGE-reference-i915_gpu_init-x60 +GNUtoo-irssi: yes, I've removed the Ids +GNUtoo-irssi: so they were regenerated +GNUtoo-irssi: the goal is not to rebase at all here +GNUtoo-irssi: that's a reference code +GNUtoo-irssi: it's not for merge either +GNUtoo-irssi: If I start modifying it, I'll need to spend time testing it again +GNUtoo-irssi: I've no time right now +GNUtoo-irssi: maybe I'll have later in theses two weeks +GNUtoo-irssi: but not right now +damo22:GNUtoo-irssi: mainboard/lenovo/x60/i915* has been removed in favour of northbridge/intel/i945/gma.c in 5320 +damo22:i thought you had changes for that +GNUtoo-irssi: yes, I know +GNUtoo-irssi: what I just pushed is a *reference code* where the GTT setup works +GNUtoo-irssi: it's old +GNUtoo-irssi: it's not meant to be merged +GNUtoo-irssi: it's not rebased +GNUtoo-irssi: it's just frozen code where it's known to work +GNUtoo-irssi: that's all + +damo22:ok +GNUtoo-irssi: it doesn't even handle backlight +GNUtoo-irssi: even with devmem2... +damo22:i'll see if i can find the gtt stuff and compare to 5320 +damo22:could be a one liner +damo22:physbase -> uma_memory_base+256*KiB +phcoder-screen:damo22: yes and rank 1 config failed +damo22:phcoder-screen: ok, so i'll get you that mchbar dump +phcoder-screen:damo22: no need yet. I found out that in another ram config my X230 fails as well. I'll investigate this first + +kmalkki:GNUtoo-irssi: please abandon the duplicates in your gerrit space +kmalkki:also any microcode files will not be removed until working copies are in 3rdparty/ + +kmalkki:we probably want to keep the old version in gerrit, with all the comments made previously + +damo22:kmalkki: all those patches are noformerge +damo22:not* +kmalkki:damo22: still they are duplicates of already reviewed patches +kmalkki:why the heck the new change-ids +damo22:maybe a git diff to a pastebin would have been better + +GNUtoo-irssi: ls +GNUtoo-irssi: oops +<uberushaximus> hunter2 +kmalkki:GNUtoo-irssi: please explain your motivation to push that stuff on gerrit +kmalkki:it is not even rebased to current but 6 months old HEAD +GNUtoo-irssi: GTT is setup badly on x60 +GNUtoo-irssi: with the recent changes from phcoder +GNUtoo-irssi: what I pushed is a version that is known to have the GTT setup correctly +GNUtoo-irssi: it's for reference +GNUtoo-irssi: so people working on i945 native GPU init would use it to fix that issue faster +GNUtoo-irssi: like diff both +GNUtoo-irssi: or something like that +GNUtoo-irssi: kmalkki: do you have a better description for the topic branch name that describe what I just said? +kmalkki:well gerrit is not for the purpose of storing references +kmalkki:most of those patches already had Change-IDs +kmalkki:now we have duplicates.. and comments can end up in either place +kmalkki:it was already a havoc with native init before +GNUtoo-irssi: ok, so instead I should remove that branch, and push on gitorious? +kmalkki:all of You working on it, try to work a setup that suits you all well +GNUtoo-irssi: briefly: it's for tracking a regression + +kmalkki:well I do not do i915 gfx stuff.. but clearly you have a lot of problems trying to keep and follow each others work +kmalkki:and what works and where the regressions have happened +PaulePanter: GNUtoo-irssi: Hi. Do you know if the amount memory reserved for i945 IGD is always constant or if that is configurable? +PaulePanter: GNUtoo-irssi: I did not see a table in the 3rd Gen datasheet. +PaulePanter: http://www.intel.com/content/dam/www/public/us/en/documents/datasheets/3rd-gen-core-family-mobile-vol-2-datasheet.pdf +GNUtoo-irssi: PaulePanter: you mean the GSM? +GNUtoo-irssi: (Graphics stolen memory) +PaulePanter: GNUtoo-irssi: Yes. + +PaulePanter: Section 2.5.33 BDSM—Base Data of Stolen Memory Register +GNUtoo-irssi: If I remmeber well it's configurable, but we use the values advised by the datasheet +GNUtoo-irssi: which are derived from the ammount of RAM +PaulePanter: This register contains the base address of graphics data stolen DRAM memory. BIOS determines the base of graphics data stolen memory by subtracting the graphics data stolen memory size (PCI Device 0 offset 52 bits 7:4) from TOLUD (PCI Device 0 offset BCh bits 31:20). +PaulePanter: GNUtoo-irssi: Yes, I am unable to find the advised values. +damo22:PaulePanter: are you sure thats the right datasheet for the cpu inside the X60? + +GNUtoo-irssi: ok +GNUtoo-irssi: I can look +PaulePanter: damo22: Not 100 %. +damo22:afaik, BSDM is something kinky in the core iX processors +GNUtoo-irssi: uma_size = 1024; +PaulePanter: Chris Wilson from the Intel graphics Linux driver team said that BDSM ist incorrectly set up. +PaulePanter: … on the i945. +PaulePanter: … by coreboot. +PaulePanter: This is Volume 2 of the Datasheet for the following products: +PaulePanter: Mobile 3rd Generation Intel ® CoreTM processor family +GNUtoo-irssi: in pci_domain_set_resources in northbridge.c +PaulePanter: Mobile Intel ® Pentium ® processor family +GNUtoo-irssi: ok +PaulePanter: Mobile Intel ® Celeron ® processor family +PaulePanter: GNUtoo-irssi: Thanks. So it is constant for now. +PaulePanter: GNUtoo-irssi: So just 1 MB graphics memory? + +damo22:i dont remember him mentioning BDSM in the bug report, but he did say the GTT was incorrectly set up? +damo22:graphics stolen stuff +GNUtoo-irssi: no it's not +GNUtoo-irssi: read the function +PaulePanter: “Stolen memory has been set up incorrectly by coreboot.” +PaulePanter: GNUtoo-irssi: Ok. +PaulePanter: GNUtoo-irssi: No idea, if you are aware of https://bugs.freedesktop.org/show_bug.cgi?id=79038 . +GNUtoo-irssi: http://paste.debian.net/101662/ +[ 0.764084] input: Video Bus as /devices/LNXSYSTM:00/device:00/PNP0A08:00/LNXVIDEO:00/input/input3 +[ 0.771023] pci 0000:00:00.0: Intel 945GM Chipset +[ 0.771075] pci 0000:00:00.0: detected gtt size: 262144K total, 262144K mappable +[ 0.771669] pci 0000:00:00.0: detected 8192K stolen memory +[ 0.771738] [drm] Memory usable by graphics device = 256M +[ 0.772124] [drm] Supports vblank timestamp caching Rev 2 (21.10.2013). +[ 0.772126] [drm] Driver supports precise vblank timestamp query. +[ 0.772133] i915 0000:00:02.0: Invalid ROM contents +[ 0.772141] [drm] failed to find VBIOS tables +[ 0.772192] [drm] GPU crash dump saved to /sys/class/drm/card0/error +[ 0.772196] [drm] GPU hangs can indicate a bug anywhere in the entire gfx stack, including userspace. +[ 0.772198] [drm] Please file a _new_ bug report on bugs.freedesktop.org against DRI -> DRM/Intel +[ 0.772200] [drm] drm/i915 developers can then reassign to the right component if it's not a kernel issue. +[ 0.772202] [drm] The gpu crash dump is required to analyze gpu hangs, so please always attach it. +[ 0.772207] vgaarb: device changed decodes: PCI:0000:00:02.0,olddecodes=io+mem,decodes=io+mem:owns=io+mem +[ 0.772217] i915: render error detected, EIR: 0x00000010 +[ 0.772224] i915: page table error +[ 0.772227] i915: PGTBL_ER: 0x00000012 +[ 0.772233] [drm:i915_report_and_clear_eir] *ERROR* EIR stuck: 0x00000010, masking +[ 0.772247] i915: render error detected, EIR: 0x00000010 +[ 0.772252] i915: page table error +[ 0.772255] i915: PGTBL_ER: 0x00000012 +[ 0.924707] [drm] initialized overlay support +[ 1.126501] fbcon: inteldrmfb (fb0) is primary device +[ 1.360027] tsc: Refined TSC clocksource calibration: 1828.749 MHz +[ 1.482148] Console: switching to colour frame buffer device 175x65 +[ 1.490507] i915 0000:00:02.0: fb0: inteldrmfb frame buffer device +[ 1.490510] i915 0000:00:02.0: registered panic notifier +[ 1.490522] [drm] Initialized i915 1.6.0 20080730 for 0000:00:02.0 on minor 0 +[ 1.491931] console [netcon0] enabled +[ 1.491933] netconsole: network logging started +[ 1.494021] ACPI: bus type USB registered +GNUtoo-irssi: that is the regression ^^^^ +GNUtoo-irssi: See PGTBL_ER +GNUtoo-irssi: The bits are documented +damo22:i have compared GNUtoo-irssi's patchset with the 5320 stuff that phcoder did, and i found that 1 line needs to be changed +GNUtoo-irssi: (I don't remember where, probably in the datasheet that applies to the more recent GPUs (sic)) + +damo22:its the base address of the gma init call + +PaulePanter: damo22: Are you going to push a patch for testing? + +damo22:but in order for it to work you need vgarom with native init, it doesnt run the rom just uses it for VBT +PaulePanter: damo22: I still not see how that should fix the error, but we’ll see. +damo22:how do i squash my commits into one patch that can be applied to 5320? +PaulePanter: damo22: Is that patch really dependent on 5320? I thought it is also needed for the current native graphics init in the tree? + +PaulePanter: damo22: `git rebase -i +PaulePanter: ` +PaulePanter: damo22: git rebase -i commit-hash-of-5320 +damo22:thanks +PaulePanter: damo22: To squash you will need to change `pick` to `f` or `s` for `fixup` or `squash`. + +damo22:i have a patch that could be tested on X60: http://review.coreboot.org/#/c/5868/ +PaulePanter: damo22: On Nehalem: +PaulePanter: src/northbridge/intel/nehalem/gma.c: intel_gma_init(conf, gtt_res->base, physbase, pio_res->base, +PaulePanter: src/northbridge/intel/nehalem/gma.c- lfb_res->base); +damo22:PaulePanter: i fail to see relevance of nehalem in i945 +PaulePanter: damo22: Hopefully the code can be written in a way that common paths are written the same. +PaulePanter: damo22: Let’s first see if the patch fixes it. + +PaulePanter: damo22: By the way, which datasheet do you think is correct for the Intel 945 IGD in the Lenovo T60 and X60? + +damo22:whichever datasheet includes 945PM (Calistoga) Graphics +damo22:is it PM or GM? +PaulePanter: damo22: I thought GM. +damo22:PM has no integrated graphics so it must be GM +PaulePanter: damo22: Document Number: 309219-006 +damo22:PaulePanter: this must be the datasheet: http://www.intel.com/content/dam/www/public/us/en/documents/datasheets/mobile-945-express-chipset-datasheet.pdf + +PaulePanter: Mobile Intel® 945 Express Chipset Family +PaulePanter: damo22: ;-) + +damo22:309219-006 is correct +PaulePanter: Graphics Stolen Memory and TSEG are within DRAM space defined under TOLUD. From +kmalkki:PaulePanter: did you go through the list of patches in your gerrit space that I suggested needed rebase? +PaulePanter: the top of low used DRAM, (G)MCH claims 1 to 64 MBs of DRAM for internal graphics if +PaulePanter: enabled. +PaulePanter: kmalkki: I thought I did go through most of them. +kmalkki:do you have the list +kmalkki:I did not keep copy :/ +kmalkki:5388 +kmalkki:that is AMR +PaulePanter: kmalkki: Don’t waste you time with it. I have a copy of your list somewhere and will go through it in the next days. +kmalkki:PaulePanter: +1 5388 +damo22:PaulePanter: its an integrated GMA 950 afaik +idwer: oh... 5388 has no priority whatsover to me +idwer: not anymore ;) + +damo22:does GM45 support in coreboot have ddr2 AND ddr3 support? + +damo22:well that means X200 could be ported with ME disabled +phcoder-screen:damo22: that's my next fun project after raminit for ivy. +* thomasg_ is now known as thomasg + +damo22:vimuser: LTN150XG-L08 is my T60 EDID string (for his T60 15" -- this is already noted below in intelvbttool results) + +vimuser: damo22: ok, i should test 5868? I understand it puts the vgarom inside but without running it (just for getting VBT tables) but latre we could replace it with something like what the X230 "Deploy VBT" does +damo22:yeah +vimuser: Let me read backlog... +damo22:vimuser: you dont need backlog, everything you need is in the 5868 commit +vimuser: how did your X60t unbricking go, damo22? +damo22:havent bothered finding my screwdrivers yet +vimuser: I need to.... tidy myself up. Back in an hour or so. +vimuser: damo22: upload a ROM for me, with 5868 and grub payload +vimuser: I'll test it for you +damo22:im not good with grub payloads +damo22:i can give you one with seabios +vimuser: ok give me that, +vimuser: also hm ok, give me your .config. I'll add grub myself +damo22:ok +damo22:vimuser: http://paste.debian.net/plain/101692 +# +# Automatically generated make config: don't edit +# coreboot version: 4.0-5614-gdb77532 +# Mon May 26 00:11:44 2014 +# + +# +# General setup +# +CONFIG_EXPERT=y +CONFIG_LOCALVERSION="" +CONFIG_CBFS_PREFIX="fallback" +CONFIG_COMPILER_GCC=y +# CONFIG_COMPILER_LLVM_CLANG is not set +# CONFIG_SCANBUILD_ENABLE is not set +# CONFIG_CCACHE is not set +# CONFIG_SCONFIG_GENPARSER is not set +CONFIG_USE_OPTION_TABLE=y +CONFIG_COMPRESS_RAMSTAGE=y +CONFIG_INCLUDE_CONFIG_FILE=y +CONFIG_EARLY_CBMEM_INIT=y +# CONFIG_DYNAMIC_CBMEM is not set +# CONFIG_COLLECT_TIMESTAMPS is not set +# CONFIG_USE_BLOBS is not set +# CONFIG_COVERAGE is not set + +# +# Mainboard +# +# CONFIG_VENDOR_AAEON is not set +# CONFIG_VENDOR_ABIT is not set +# CONFIG_VENDOR_ADLINK is not set +# CONFIG_VENDOR_ADVANSUS is not set +# CONFIG_VENDOR_ADVANTECH is not set +# CONFIG_VENDOR_AMD is not set +# CONFIG_VENDOR_AOPEN is not set +# CONFIG_VENDOR_ARIMA is not set +# CONFIG_VENDOR_ARTECGROUP is not set +# CONFIG_VENDOR_ASI is not set +# CONFIG_VENDOR_ASROCK is not set +# CONFIG_VENDOR_ASUS is not set +# CONFIG_VENDOR_A_TREND is not set +# CONFIG_VENDOR_AVALUE is not set +# CONFIG_VENDOR_AXUS is not set +# CONFIG_VENDOR_AZZA is not set +# CONFIG_VENDOR_BACHMANN is not set +# CONFIG_VENDOR_BCOM is not set +# CONFIG_VENDOR_BIFFEROS is not set +# CONFIG_VENDOR_BIOSTAR is not set +# CONFIG_VENDOR_BROADCOM is not set +# CONFIG_VENDOR_COMPAQ is not set +# CONFIG_VENDOR_CUBIETECH is not set +# CONFIG_VENDOR_DIGITALLOGIC is not set +# CONFIG_VENDOR_DMP is not set +# CONFIG_VENDOR_EAGLELION is not set +# CONFIG_VENDOR_ECS is not set +# CONFIG_VENDOR_EMULATION is not set +# CONFIG_VENDOR_GETAC is not set +# CONFIG_VENDOR_GIGABYTE is not set +# CONFIG_VENDOR_GIZMOSPHERE is not set +# CONFIG_VENDOR_GOOGLE is not set +# CONFIG_VENDOR_HP is not set +# CONFIG_VENDOR_IBASE is not set +# CONFIG_VENDOR_IBM is not set +# CONFIG_VENDOR_IEI is not set +# CONFIG_VENDOR_INTEL is not set +# CONFIG_VENDOR_IWAVE is not set +# CONFIG_VENDOR_IWILL is not set +# CONFIG_VENDOR_JETWAY is not set +# CONFIG_VENDOR_KONTRON is not set +# CONFIG_VENDOR_LANNER is not set +CONFIG_VENDOR_LENOVO=y +# CONFIG_VENDOR_LINUTOP is not set +# CONFIG_VENDOR_LIPPERT is not set +# CONFIG_VENDOR_MITAC is not set +# CONFIG_VENDOR_MSI is not set +# CONFIG_VENDOR_NEC is not set +# CONFIG_VENDOR_NEWISYS is not set +# CONFIG_VENDOR_NOKIA is not set +# CONFIG_VENDOR_NVIDIA is not set +# CONFIG_VENDOR_PCENGINES is not set +# CONFIG_VENDOR_RCA is not set +# CONFIG_VENDOR_RODA is not set +# CONFIG_VENDOR_SAMSUNG is not set +# CONFIG_VENDOR_SIEMENS is not set +# CONFIG_VENDOR_SOYO is not set +# CONFIG_VENDOR_SUNW is not set +# CONFIG_VENDOR_SUPERMICRO is not set +# CONFIG_VENDOR_TECHNEXION is not set +# CONFIG_VENDOR_TECHNOLOGIC is not set +# CONFIG_VENDOR_TELEVIDEO is not set +# CONFIG_VENDOR_TI is not set +# CONFIG_VENDOR_THOMSON is not set +# CONFIG_VENDOR_TRAVERSE is not set +# CONFIG_VENDOR_TYAN is not set +# CONFIG_VENDOR_VIA is not set +# CONFIG_VENDOR_WINENT is not set +# CONFIG_VENDOR_WYSE is not set +CONFIG_BOARD_SPECIFIC_OPTIONS=y +CONFIG_MAINBOARD_DIR="lenovo/x60" +CONFIG_MAINBOARD_PART_NUMBER="ThinkPad X60 / X60s" +CONFIG_IRQ_SLOT_COUNT=18 +CONFIG_MAINBOARD_VENDOR="Lenovo" +CONFIG_MAX_CPUS=2 +CONFIG_RAMTOP=0x200000 +CONFIG_HEAP_SIZE=0x4000 +CONFIG_RAMBASE=0x100000 +CONFIG_VGA_BIOS_ID="8086,27a2" +CONFIG_DRIVERS_PS2_KEYBOARD=y +CONFIG_ONBOARD_VGA_IS_PRIMARY=y +CONFIG_VGA_BIOS=y +# CONFIG_CONSOLE_POST is not set +# CONFIG_UDELAY_IO is not set +CONFIG_DCACHE_RAM_BASE=0xffdf8000 +CONFIG_DCACHE_RAM_SIZE=0x8000 +CONFIG_SERIAL_CPU_INIT=y +CONFIG_ACPI_SSDTX_NUM=0 +CONFIG_VGA_BIOS_FILE="vgabios.bin" +# CONFIG_PCI_64BIT_PREF_MEM is not set +CONFIG_MMCONF_BASE_ADDRESS=0xf0000000 +CONFIG_ID_SECTION_OFFSET=0x80 +# CONFIG_BOARD_EMULATION_QEMU_X86_I440FX is not set +# CONFIG_BOARD_EMULATION_QEMU_X86_Q35 is not set +# CONFIG_BOARD_EMULATION_QEMU_ARMV7 is not set +CONFIG_STACK_SIZE=0x1000 +CONFIG_XIP_ROM_SIZE=0x10000 +CONFIG_MMCONF_SUPPORT_DEFAULT=y +# CONFIG_VGA is not set +CONFIG_BOARD_LENOVO_X60=y +# CONFIG_BOARD_LENOVO_X201 is not set +# CONFIG_BOARD_LENOVO_X230 is not set +# CONFIG_BOARD_LENOVO_T60 is not set +CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="LENOVO" +CONFIG_SEABIOS_PS2_TIMEOUT=3000 +CONFIG_MAINBOARD_VERSION="1.0" +CONFIG_CPU_ADDR_BITS=32 +CONFIG_CACHE_ROM_SIZE_OVERRIDE=0 +# CONFIG_POWER_BUTTON_FORCE_ENABLE is not set +CONFIG_LOGICAL_CPUS=y +CONFIG_IOAPIC=y +CONFIG_SMP=y +CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 +# CONFIG_USBDEBUG is not set +CONFIG_MAXIMUM_SUPPORTED_FREQUENCY=0 +CONFIG_BOARD_ROMSIZE_KB_2048=y +# CONFIG_COREBOOT_ROMSIZE_KB_64 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_128 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set +CONFIG_COREBOOT_ROMSIZE_KB_2048=y +# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_8192 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set +CONFIG_COREBOOT_ROMSIZE_KB=2048 +CONFIG_ROM_SIZE=0x200000 +CONFIG_MAINBOARD_SERIAL_NUMBER="123456789" +CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="ThinkPad X60 / X60s" +CONFIG_ARCH_X86=y +# CONFIG_ARCH_ARMV7 is not set + +# +# Architecture (x86) +# +CONFIG_X86_ARCH_OPTIONS=y +CONFIG_AP_IN_SIPI_WAIT=y +# CONFIG_SIPI_VECTOR_IN_ROM is not set +CONFIG_MAX_REBOOT_CNT=3 +CONFIG_NUM_IPI_STARTS=2 +CONFIG_X86_BOOTBLOCK_SIMPLE=y +# CONFIG_X86_BOOTBLOCK_NORMAL is not set +CONFIG_BOOTBLOCK_SOURCE="bootblock_simple.c" +# CONFIG_UPDATE_IMAGE is not set +# CONFIG_ROMCC is not set +CONFIG_PC80_SYSTEM=y +CONFIG_BOOTBLOCK_NORTHBRIDGE_INIT="northbridge/intel/i945/bootblock.c" +CONFIG_HAVE_CMOS_DEFAULT=y +CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default" +CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT="southbridge/intel/i82801gx/bootblock.c" +CONFIG_IOAPIC_INTERRUPTS_ON_FSB=y +# CONFIG_IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS is not set +CONFIG_HPET_ADDRESS=0xfed00000 +CONFIG_HAVE_ARCH_MEMSET=y +CONFIG_HAVE_ARCH_MEMCPY=y +CONFIG_HAVE_ARCH_MEMMOVE=y +# CONFIG_MAINBOARD_HAS_CHROMEOS is not set + +# +# Chipset +# + +# +# CPU +# +CONFIG_SOCKET_SPECIFIC_OPTIONS=y +# CONFIG_CPU_AMD_AGESA is not set +CONFIG_HAVE_INIT_TIMER=y +CONFIG_HIGH_SCRATCH_MEMORY_SIZE=0x0 +CONFIG_CPU_INTEL_MODEL_6EX=y +CONFIG_CPU_INTEL_MODEL_6FX=y +CONFIG_SMM_TSEG_SIZE=0 +CONFIG_CPU_INTEL_SOCKET_MFCPGA478=y +CONFIG_SSE2=y +# CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE is not set +# CONFIG_CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED is not set +CONFIG_UDELAY_LAPIC=y +CONFIG_LAPIC_MONOTONIC_TIMER=y +# CONFIG_UDELAY_TSC is not set +# CONFIG_UDELAY_TIMER2 is not set +# CONFIG_TSC_CALIBRATE_WITH_IO is not set +# CONFIG_TSC_SYNC_LFENCE is not set +CONFIG_TSC_SYNC_MFENCE=y +# CONFIG_SMM_TSEG is not set +# CONFIG_SMM_MODULES is not set +# CONFIG_X86_AMD_FIXED_MTRRS is not set +# CONFIG_PARALLEL_MP is not set +# CONFIG_BACKUP_DEFAULT_SMM_REGION is not set +CONFIG_CACHE_AS_RAM=y +CONFIG_AP_SIPI_VECTOR=0xfffff000 +CONFIG_MMX=y +CONFIG_SSE=y +CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y +CONFIG_CPU_MICROCODE_ADDED_DURING_BUILD=y +CONFIG_CPU_MICROCODE_CBFS_GENERATE=y +# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL is not set +# CONFIG_CPU_MICROCODE_CBFS_NONE is not set + +# +# Northbridge +# +CONFIG_VIDEO_MB=0 +# CONFIG_NORTHBRIDGE_AMD_AGESA is not set +# CONFIG_AMD_NB_CIMX is not set +# CONFIG_NORTHBRIDGE_AMD_CIMX_RD890 is not set +CONFIG_NORTHBRIDGE_SPECIFIC_OPTIONS=y +CONFIG_NORTHBRIDGE_INTEL_I945=y +# CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GC is not set +CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM=y +CONFIG_CHANNEL_XOR_RANDOMIZATION=y +# CONFIG_OVERRIDE_CLOCK_DISABLE is not set +# CONFIG_CHECK_SLFRCS_ON_RESUME is not set +CONFIG_CBFS_SIZE=0x200000 +CONFIG_HPET_MIN_TICKS=0x80 +CONFIG_MAX_PIRQ_LINKS=4 + +# +# Southbridge +# +CONFIG_EHCI_BAR=0xfef00000 +# CONFIG_AMD_SB_CIMX is not set +# CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800 is not set +# CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900 is not set +CONFIG_AMD_SB_SPI_TX_LEN=4 +# CONFIG_SPI_FLASH is not set +CONFIG_SOUTHBRIDGE_INTEL_COMMON=y +CONFIG_SOUTHBRIDGE_INTEL_I82801GX=y +CONFIG_SOUTHBRIDGE_RICOH_RL5C476=y + +# +# Super I/O +# +CONFIG_SUPERIO_NSC_PC87382=y +CONFIG_SUPERIO_NSC_PC87392=y + +# +# Embedded Controllers +# +CONFIG_EC_ACPI=y +CONFIG_EC_LENOVO_H8=y +CONFIG_H8_DOCK_EARLY_INIT=y +CONFIG_EC_LENOVO_PMH7=y + +# +# SoC +# + +# +# Devices +# +CONFIG_MAINBOARD_HAS_NATIVE_VGA_INIT=y +# CONFIG_MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG is not set +CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT=y +# CONFIG_VGA_ROM_RUN is not set +# CONFIG_ON_DEVICE_ROM_RUN is not set +# CONFIG_MULTIPLE_VGA_ADAPTERS is not set +CONFIG_PCI=y +# CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT is not set +CONFIG_PCIX_PLUGIN_SUPPORT=y +CONFIG_PCIEXP_PLUGIN_SUPPORT=y +CONFIG_AGP_PLUGIN_SUPPORT=y +CONFIG_CARDBUS_PLUGIN_SUPPORT=y +# CONFIG_AZALIA_PLUGIN_SUPPORT is not set +# CONFIG_PCIEXP_COMMON_CLOCK is not set +# CONFIG_PCIEXP_ASPM is not set +CONFIG_PCI_BUS_SEGN_BITS=0 + +# +# VGA BIOS +# + +# +# Display +# + +# +# PXE ROM +# +# CONFIG_PXE_ROM is not set +CONFIG_SUBSYSTEM_VENDOR_ID=0x0000 +CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 + +# +# Generic Drivers +# +# CONFIG_DRIVERS_I2C_RTD2132 is not set +CONFIG_DRIVERS_ICS_954309=y +# CONFIG_INTEL_DP is not set +# CONFIG_INTEL_DDI is not set +CONFIG_INTEL_EDID=y +# CONFIG_IPMI_KCS is not set +# CONFIG_DRIVER_MAXIM_MAX77686 is not set +# CONFIG_DRIVERS_OXFORD_OXPCIE is not set +# CONFIG_DRIVER_PARADE_PS8625 is not set +# CONFIG_TPM is not set +# CONFIG_RTL8168_ROM_DISABLE is not set +# CONFIG_DRIVERS_SIL_3114 is not set +# CONFIG_DRIVER_TI_TPS65090 is not set +CONFIG_HAVE_UART_IO_MAPPED=y +# CONFIG_HAVE_UART_MEMORY_MAPPED is not set +# CONFIG_HAVE_UART_SPECIAL is not set +# CONFIG_DRIVER_XPOWERS_AXP209 is not set +CONFIG_MMCONF_SUPPORT=y + +# +# Console +# +CONFIG_EARLY_CONSOLE=y +CONFIG_SQUELCH_EARLY_SMP=y +CONFIG_CONSOLE_SERIAL=y +CONFIG_CONSOLE_SERIAL8250=y +CONFIG_CONSOLE_SERIAL_COM1=y +# CONFIG_CONSOLE_SERIAL_COM2 is not set +# CONFIG_CONSOLE_SERIAL_COM3 is not set +# CONFIG_CONSOLE_SERIAL_COM4 is not set +CONFIG_TTYS0_BASE=0x3f8 +CONFIG_CONSOLE_SERIAL_115200=y +# CONFIG_CONSOLE_SERIAL_57600 is not set +# CONFIG_CONSOLE_SERIAL_38400 is not set +# CONFIG_CONSOLE_SERIAL_19200 is not set +# CONFIG_CONSOLE_SERIAL_9600 is not set +CONFIG_TTYS0_BAUD=115200 +CONFIG_TTYS0_LCS=3 +# CONFIG_SPKMODEM is not set +CONFIG_HAVE_USBDEBUG=y +# CONFIG_HAVE_USBDEBUG_OPTIONS is not set +# CONFIG_CONSOLE_NE2K is not set +# CONFIG_CONSOLE_CBMEM is not set +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8=y +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set +# CONFIG_NO_POST is not set +# CONFIG_CMOS_POST is not set +CONFIG_IO_POST=y +CONFIG_IO_POST_PORT=0x80 +CONFIG_HAVE_ACPI_RESUME=y +# CONFIG_HAVE_ACPI_SLIC is not set +CONFIG_HAVE_HARD_RESET=y +CONFIG_HAVE_MONOTONIC_TIMER=y +# CONFIG_TIMER_QUEUE is not set +CONFIG_HAVE_OPTION_TABLE=y +# CONFIG_PIRQ_ROUTE is not set +CONFIG_HAVE_SMI_HANDLER=y +# CONFIG_PCI_IO_CFG_EXT is not set +CONFIG_USE_WATCHDOG_ON_BOOT=y +CONFIG_GFXUMA=y +# CONFIG_RELOCATABLE_MODULES is not set +# CONFIG_HAVE_REFCODE_BLOB is not set +CONFIG_HAVE_ACPI_TABLES=y +CONFIG_HAVE_MP_TABLE=y +CONFIG_HAVE_PIRQ_TABLE=y + +# +# System tables +# +CONFIG_GENERATE_ACPI_TABLES=y +CONFIG_GENERATE_MP_TABLE=y +CONFIG_GENERATE_PIRQ_TABLE=y +CONFIG_GENERATE_SMBIOS_TABLES=y + +# +# Payload +# +# CONFIG_PAYLOAD_NONE is not set +# CONFIG_PAYLOAD_ELF is not set +# CONFIG_PAYLOAD_LINUX is not set +CONFIG_PAYLOAD_SEABIOS=y +# CONFIG_PAYLOAD_FILO is not set +# CONFIG_PAYLOAD_GRUB2 is not set +# CONFIG_PAYLOAD_TIANOCORE is not set +CONFIG_SEABIOS_STABLE=y +# CONFIG_SEABIOS_MASTER is not set +CONFIG_PAYLOAD_FILE="$(obj)/seabios/out/bios.bin.elf" +CONFIG_COMPRESSED_PAYLOAD_LZMA=y + +# +# Debugging +# +# CONFIG_GDB_STUB is not set +# CONFIG_DEBUG_CBFS is not set +CONFIG_HAVE_DEBUG_RAM_SETUP=y +# CONFIG_DEBUG_RAM_SETUP is not set +# CONFIG_HAVE_DEBUG_CAR is not set +# CONFIG_DEBUG_PIRQ is not set +# CONFIG_HAVE_DEBUG_SMBUS is not set +# CONFIG_DEBUG_SMI is not set +# CONFIG_DEBUG_SMM_RELOCATION is not set +# CONFIG_DEBUG_MALLOC is not set +# CONFIG_DEBUG_ACPI is not set +# CONFIG_TRACE is not set +# CONFIG_ENABLE_APIC_EXT_ID is not set +CONFIG_WARNINGS_ARE_ERRORS=y +# CONFIG_POWER_BUTTON_DEFAULT_ENABLE is not set +# CONFIG_POWER_BUTTON_DEFAULT_DISABLE is not set +# CONFIG_POWER_BUTTON_FORCE_DISABLE is not set +# CONFIG_POWER_BUTTON_IS_OPTIONAL is not set + +damo22:you need to still add the vgabios filename +damo22:CONFIG_VGA_BIOS_FILE="vgabios.bin" is the current setting +damo22:# CONFIG_CONSOLE_CBMEM is not set woops + +vimuser: damo22 » register "gpu_lvds_is_dual_channel" = "1" +vimuser: on x60/devicetree.cb +damo22:vimuser: well check your VBT i think its correct though +vimuser: so 0 was wrong? +damo22:it might depend on panel + +vimuser: Oh +vimuser: I get it now. +vimuser: I didn't see any code in 5868 that executes anything from the vgarom but, +vimuser: you set coreboot to load it into memory, but not execute it. +vimuser: I thought "load" only meant put it in cbfs +vimuser: is this a correct assessment? +vimuser: To let kernel find vbt tables. +vimuser: And then we "fake" it later (withotu vga rom loaded). +vimuser: damo22: are you testing 5868 on your X60t? +damo22:vimuser: its to make linux kernel detect lvds after native init, but if you can also test coreboot native framebuffer with grub too, that would be handy + +vimuser: So, vgarom has nothing to do with that patch. +vimuser: ? +vimuser: All I see is a change of stolen memory address, and the backlight values added +damo22:vimuser: its tricky because the final vgabios in memory changes depending on the panel, because vgarom is self modifying + +vimuser: So should I include the vgarunning.bin instead of vgabios.bin ? +damo22:yes + +damo22:vimuser: if you can load grub as payload and you see something, its a success +vimuser: damo22: the problem is, without that patch I just use 5320 as-is, and I see grub as payload already. +vimuser: Hence my question above. +damo22:vimuser: also, if you can boot into linux after that and dont get any error messages from drm module, its a double success +vimuser: Which error messages (besides "Invalid ROM contents") am I looking for? +damo22:vimuser: stuff like, page fault +vimuser: And should I enable any specific debugging options (such as drm.debug=0x06) +damo22:yes that would help +vimuser: Ok: which logs do you want? +vimuser: I'll upload it for your reference +damo22:vimuser: kernel boot log and Xorg.0.log, coreboot log if possible +vimuser: probably kern.log and Xorg.0.log +vimuser: coreboot log is possible, i have dock. +vimuser: anything else? +damo22:that is all, thanks +vimuser: ok. will do. + +vimuser: damo22: I could test this on T60 aswell by cherry picking 5345, right? +damo22:vimuser: idk +vimuser: (and addinf backlight value to deivcetree) +vimuser: We should devise a way to test this on T60 aswell. +damo22:vimuser: lets just see if the x60 fix works + +damo22:it still needs work if the test passes +vimuser: Ok but, you just have that one line changed in gma.c, and backlight value changed it x60/devicetree.cb +damo22:yes +damo22:phcoder did most of the work +vimuser: So, I could run this same test on T60 by cherry picking 5345 on top of 5868, changing t60/devicetree.cb's backlight value and including T60 runningvga.bin and having that load (but not execute) +damo22:its a small bug i think +vimuser: I will do that above, after X60 is tested. +damo22:vimuser: youre always talking about more and more combinations of tests, lets just get one right +vimuser: Yes. Just a thought. We'll test X60 exclusively. T60 can easily be tested later. +vimuser: Ok..... back soon. I'll get you the results you wanted. I'll be using 3.14.4 (the one samnob made). +damo22:thanks + +vimuser: We should do this with the latest runningvga.bin (from extracting with dd on the latest vgabios.bin) +vimuser: My one is older +damo22:vimuser: version number of vgabios is irrelevant if it was taken from a lenovo bios that used to run on your machine, and since pulled from ram +damo22:ie, it should have the correct VBT values +damo22:for your machine + + + +</pre> +</p> + diff --git a/docs/future/dumps/logs-t400-bios2.02-ec1.01/biosdecode.log b/docs/future/dumps/logs-t400-bios2.02-ec1.01/biosdecode.log @@ -0,0 +1,24 @@ +# biosdecode 2.12 +VPD present. + BIOS Build ID: 7UET56WW + Box Serial Number: L3BLN3R + Motherboard Serial Number: VF26F91C27K + Machine Type/Model: 6475GE2 +SMBIOS 2.4 present. + Structure Table Length: 2469 bytes + Structure Table Address: 0x000E0010 + Number Of Structures: 74 + Maximum Structure Size: 120 bytes +BIOS32 Service Directory present. + Revision: 0 + Calling Interface Address: 0x000FDC80 +ACPI 2.0 present. + OEM Identifier: LENOVO + RSD Table 32-bit Address: 0xBCB6A54A + XSD Table 64-bit Address: 0x00000000BCB6A5B6 +PNP BIOS 1.0 present. + Event Notification: Not Supported + Real Mode 16-bit Code Address: E19B:1934 + Real Mode 16-bit Data Address: 0040:0000 + 16-bit Protected Mode Code Address: 0x000F8AD1 + 16-bit Protected Mode Data Address: 0x00000400 diff --git a/docs/future/dumps/logs-t400-bios2.02-ec1.01/codec#0 b/docs/future/dumps/logs-t400-bios2.02-ec1.01/codec#0 @@ -0,0 +1,208 @@ +Codec: Conexant CX20561 (Hermosa) +Address: 0 +AFG Function Id: 0x1 (unsol 1) +MFG Function Id: 0x2 (unsol 1) +Vendor Id: 0x14f15051 +Subsystem Id: 0x17aa211c +Revision Id: 0x100000 +Modem Function Group: 0x2 +Default PCM: + rates [0x160]: 44100 48000 96000 + bits [0xe]: 16 20 24 + formats [0x1]: PCM +Default Amp-In caps: N/A +Default Amp-Out caps: N/A +State of AFG node 0x01: + Power states: D0 D1 D2 D3 CLKSTOP + Power: setting=D0, actual=D0 +GPIO: io=4, o=0, i=0, unsolicited=1, wake=0 + IO[0]: enable=0, dir=0, wake=0, sticky=0, data=0, unsol=0 + IO[1]: enable=0, dir=0, wake=0, sticky=0, data=0, unsol=0 + IO[2]: enable=0, dir=0, wake=0, sticky=0, data=0, unsol=0 + IO[3]: enable=0, dir=0, wake=0, sticky=0, data=0, unsol=0 +Node 0x10 [Audio Output] wcaps 0xc1d: Stereo Amp-Out R/L + Control: name="Speaker Playback Volume", index=0, device=0 + ControlAmp: chs=3, dir=Out, idx=0, ofs=0 + Control: name="Speaker Playback Switch", index=0, device=0 + ControlAmp: chs=3, dir=Out, idx=0, ofs=0 + Device: name="CX20561 Analog", type="Audio", device=0 + Amp-Out caps: ofs=0x4a, nsteps=0x4a, stepsize=0x03, mute=0 + Amp-Out vals: [0x00 0x00] + Converter: stream=8, channel=0 + PCM: + rates [0x560]: 44100 48000 96000 192000 + bits [0xe]: 16 20 24 + formats [0x1]: PCM + Power states: D0 D1 D2 D3 + Power: setting=D0, actual=D0 +Node 0x11 [Audio Output] wcaps 0xc1d: Stereo Amp-Out R/L + Control: name="Headphone Playback Volume", index=0, device=0 + ControlAmp: chs=3, dir=Out, idx=0, ofs=0 + Control: name="Headphone Playback Switch", index=0, device=0 + ControlAmp: chs=3, dir=Out, idx=0, ofs=0 + Amp-Out caps: ofs=0x4a, nsteps=0x4a, stepsize=0x03, mute=0 + Amp-Out vals: [0x00 0x00] + Converter: stream=8, channel=0 + PCM: + rates [0x560]: 44100 48000 96000 192000 + bits [0xe]: 16 20 24 + formats [0x1]: PCM + Power states: D0 D1 D2 D3 + Power: setting=D0, actual=D0 +Node 0x12 [Audio Output] wcaps 0x211: Stereo Digital + Control: name="IEC958 Playback Con Mask", index=0, device=0 + Control: name="IEC958 Playback Pro Mask", index=0, device=0 + Control: name="IEC958 Playback Default", index=0, device=0 + Control: name="IEC958 Playback Switch", index=0, device=0 + Control: name="IEC958 Default PCM Playback Switch", index=0, device=0 + Device: name="CX20561 Digital", type="SPDIF", device=1 + Converter: stream=8, channel=0 + Digital: + Digital category: 0x0 + IEC Coding Type: 0x0 + PCM: + rates [0x160]: 44100 48000 96000 + bits [0xe]: 16 20 24 + formats [0x5]: PCM AC3 +Node 0x13 [Beep Generator Widget] wcaps 0x70000c: Mono Amp-Out + Control: name="Beep Playback Volume", index=0, device=0 + ControlAmp: chs=1, dir=Out, idx=0, ofs=0 + Control: name="Beep Playback Switch", index=0, device=0 + ControlAmp: chs=1, dir=Out, idx=0, ofs=0 + Amp-Out caps: ofs=0x03, nsteps=0x03, stepsize=0x17, mute=0 + Amp-Out vals: [0x00] +Node 0x14 [Audio Input] wcaps 0x100d1b: Stereo Amp-In R/L + Device: name="CX20561 Analog", type="Audio", device=0 + Amp-In caps: ofs=0x4a, nsteps=0x50, stepsize=0x03, mute=0 + Amp-In vals: [0x50 0x50] [0x50 0x50] + Converter: stream=4, channel=0 + SDI-Select: 0 + PCM: + rates [0x160]: 44100 48000 96000 + bits [0xe]: 16 20 24 + formats [0x1]: PCM + Power states: D0 D1 D2 D3 + Power: setting=D0, actual=D0 + Connection: 2 + 0x1d* 0x17 +Node 0x15 [Audio Input] wcaps 0x100d1b: Stereo Amp-In R/L + Control: name="Capture Volume", index=0, device=0 + ControlAmp: chs=3, dir=In, idx=1, ofs=0 + Amp-In caps: ofs=0x4a, nsteps=0x50, stepsize=0x03, mute=0 + Amp-In vals: [0x50 0x50] + Converter: stream=0, channel=0 + SDI-Select: 0 + PCM: + rates [0x160]: 44100 48000 96000 + bits [0xe]: 16 20 24 + formats [0x1]: PCM + Power states: D0 D1 D2 D3 + Power: setting=D0, actual=D0 + Connection: 1 + 0x18 +Node 0x16 [Pin Complex] wcaps 0x400581: Stereo + Control: name="Headphone Jack", index=0, device=0 + Pincap 0x0000001c: OUT HP Detect + Pin Default 0x022140f0: [Jack] HP Out at Ext Front + Conn = 1/8, Color = Green + DefAssociation = 0xf, Sequence = 0x0 + Pin-ctls: 0xc0: OUT HP + Unsolicited: tag=02, enabled=1 + Power states: D0 D1 D2 D3 + Power: setting=D0, actual=D0 + Connection: 2 + 0x10 0x11* +Node 0x17 [Pin Complex] wcaps 0x40048b: Stereo Amp-In + Control: name="Dock Mic Boost Volume", index=0, device=0 + ControlAmp: chs=3, dir=In, idx=0, ofs=0 + Control: name="Dock Mic Jack", index=0, device=0 + Amp-In caps: ofs=0x00, nsteps=0x04, stepsize=0x27, mute=0 + Amp-In vals: [0x00 0x00] + Pincap 0x00001224: IN Detect + Vref caps: 50 80 + Pin Default 0x61a190f0: [N/A] Mic at Sep Rear + Conn = 1/8, Color = Pink + DefAssociation = 0xf, Sequence = 0x0 + Pin-ctls: 0x24: IN VREF_80 + Unsolicited: tag=03, enabled=1 + Power states: D0 D1 D2 D3 + Power: setting=D0, actual=D0 +Node 0x18 [Pin Complex] wcaps 0x40048b: Stereo Amp-In + Control: name="Mic Boost Volume", index=0, device=0 + ControlAmp: chs=3, dir=In, idx=0, ofs=0 + Control: name="Mic Jack", index=0, device=0 + Amp-In caps: ofs=0x00, nsteps=0x04, stepsize=0x27, mute=0 + Amp-In vals: [0x00 0x00] + Pincap 0x00001224: IN Detect + Vref caps: 50 80 + Pin Default 0x02a190f0: [Jack] Mic at Ext Front + Conn = 1/8, Color = Pink + DefAssociation = 0xf, Sequence = 0x0 + Pin-ctls: 0x24: IN VREF_80 + Unsolicited: tag=04, enabled=1 + Power states: D0 D1 D2 D3 + Power: setting=D0, actual=D0 +Node 0x19 [Pin Complex] wcaps 0x400581: Stereo + Control: name="Dock Headphone Jack", index=0, device=0 + Pincap 0x00000014: OUT Detect + Pin Default 0x40f000f0: [N/A] Other at Ext N/A + Conn = Unknown, Color = Unknown + DefAssociation = 0xf, Sequence = 0x0 + Pin-ctls: 0x40: OUT + Unsolicited: tag=01, enabled=1 + Power states: D0 D1 D2 D3 + Power: setting=D0, actual=D0 + Connection: 2 + 0x10 0x11* +Node 0x1a [Pin Complex] wcaps 0x400501: Stereo + Control: name="Speaker Phantom Jack", index=0, device=0 + Pincap 0x00010010: OUT EAPD + EAPD 0x2: EAPD + Pin Default 0x901701f0: [Fixed] Speaker at Int N/A + Conn = Analog, Color = Unknown + DefAssociation = 0xf, Sequence = 0x0 + Misc = NO_PRESENCE + Pin-ctls: 0x40: OUT + Power states: D0 D1 D2 D3 + Power: setting=D0, actual=D0 + Connection: 2 + 0x10* 0x11 +Node 0x1b [Pin Complex] wcaps 0x400500: Mono + Pincap 0x00010010: OUT EAPD + EAPD 0x2: EAPD + Pin Default 0x40f001f0: [N/A] Other at Ext N/A + Conn = Unknown, Color = Unknown + DefAssociation = 0xf, Sequence = 0x0 + Misc = NO_PRESENCE + Pin-ctls: 0x40: OUT + Power states: D0 D1 D2 D3 + Power: setting=D0, actual=D0 + Connection: 2 + 0x10* 0x11 +Node 0x1c [Pin Complex] wcaps 0x400701: Stereo Digital + Control: name="SPDIF Phantom Jack", index=0, device=0 + Pincap 0x00000010: OUT + Pin Default 0x40f001f0: [N/A] Other at Ext N/A + Conn = Unknown, Color = Unknown + DefAssociation = 0xf, Sequence = 0x0 + Misc = NO_PRESENCE + Pin-ctls: 0x40: OUT + Power states: D0 D1 D2 D3 + Power: setting=D0, actual=D0 + Connection: 1 + 0x12 +Node 0x1d [Pin Complex] wcaps 0x40040b: Stereo Amp-In + Control: name="Internal Mic Boost Volume", index=0, device=0 + ControlAmp: chs=3, dir=In, idx=0, ofs=0 + Control: name="Internal Mic Phantom Jack", index=0, device=0 + Amp-In caps: ofs=0x00, nsteps=0x04, stepsize=0x2f, mute=0 + Amp-In vals: [0x00 0x00] + Pincap 0x00000020: IN + Pin Default 0x90a601f0: [Fixed] Mic at Int N/A + Conn = Digital, Color = Unknown + DefAssociation = 0xf, Sequence = 0x0 + Misc = NO_PRESENCE + Pin-ctls: 0x20: IN + Power states: D0 D1 D2 D3 + Power: setting=D0, actual=D0 +Node 0x1e [Vendor Defined Widget] wcaps 0xf00000: Mono diff --git a/docs/future/dumps/logs-t400-bios2.02-ec1.01/cpuinfo.log b/docs/future/dumps/logs-t400-bios2.02-ec1.01/cpuinfo.log @@ -0,0 +1,52 @@ +processor : 0 +vendor_id : GenuineIntel +cpu family : 6 +model : 23 +model name : Intel(R) Core(TM)2 Duo CPU P8400 @ 2.26GHz +stepping : 6 +microcode : 0x60c +cpu MHz : 1600.000 +cache size : 3072 KB +physical id : 0 +siblings : 2 +core id : 0 +cpu cores : 2 +apicid : 0 +initial apicid : 0 +fpu : yes +fpu_exception : yes +cpuid level : 10 +wp : yes +flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe syscall nx lm constant_tsc arch_perfmon pebs bts nopl aperfmperf pni dtes64 monitor ds_cpl vmx smx est tm2 ssse3 cx16 xtpr pdcm sse4_1 lahf_lm dtherm tpr_shadow vnmi flexpriority +bogomips : 4521.76 +clflush size : 64 +cache_alignment : 64 +address sizes : 36 bits physical, 48 bits virtual +power management: + +processor : 1 +vendor_id : GenuineIntel +cpu family : 6 +model : 23 +model name : Intel(R) Core(TM)2 Duo CPU P8400 @ 2.26GHz +stepping : 6 +microcode : 0x60c +cpu MHz : 1600.000 +cache size : 3072 KB +physical id : 0 +siblings : 2 +core id : 1 +cpu cores : 2 +apicid : 1 +initial apicid : 1 +fpu : yes +fpu_exception : yes +cpuid level : 10 +wp : yes +flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe syscall nx lm constant_tsc arch_perfmon pebs bts nopl aperfmperf pni dtes64 monitor ds_cpl vmx smx est tm2 ssse3 cx16 xtpr pdcm sse4_1 lahf_lm dtherm tpr_shadow vnmi flexpriority +bogomips : 4521.76 +clflush size : 64 +cache_alignment : 64 +address sizes : 36 bits physical, 48 bits virtual +power management: + diff --git a/docs/future/dumps/logs-t400-bios2.02-ec1.01/dmesg.log b/docs/future/dumps/logs-t400-bios2.02-ec1.01/dmesg.log @@ -0,0 +1,1042 @@ +[ 0.000000] Initializing cgroup subsys cpuset +[ 0.000000] Initializing cgroup subsys cpu +[ 0.000000] Initializing cgroup subsys cpuacct +[ 0.000000] Linux version 3.13.0-39-lowlatency (root@devel.trisquel.info) (gcc version 4.8.2 (Ubuntu 4.8.2-19ubuntu1) ) #66+7.0trisquel2 SMP PREEMPT Wed Oct 29 17:10:10 UTC 2014 (Ubuntu 3.13.0-39.66+7.0trisquel2-lowlatency 3.13.11.8-gnu) +[ 0.000000] Command line: BOOT_IMAGE=/boot/vmlinuz-3.13.0-39-lowlatency root=UUID=35246665-9714-42dc-8ff4-580d4cf85131 ro nomdmonddf nomdmonisw nomdmonddf nomdmonisw +[ 0.000000] KERNEL supported cpus: +[ 0.000000] Intel GenuineIntel +[ 0.000000] AMD AuthenticAMD +[ 0.000000] Centaur CentaurHauls +[ 0.000000] Disabled fast string operations +[ 0.000000] e820: BIOS-provided physical RAM map: +[ 0.000000] BIOS-e820: [mem 0x0000000000000000-0x000000000009ebff] usable +[ 0.000000] BIOS-e820: [mem 0x000000000009ec00-0x000000000009ffff] reserved +[ 0.000000] BIOS-e820: [mem 0x00000000000dc000-0x00000000000fffff] reserved +[ 0.000000] BIOS-e820: [mem 0x0000000000100000-0x00000000bc6a0fff] usable +[ 0.000000] BIOS-e820: [mem 0x00000000bc6a1000-0x00000000bc6a6fff] reserved +[ 0.000000] BIOS-e820: [mem 0x00000000bc6a7000-0x00000000bc7b6fff] usable +[ 0.000000] BIOS-e820: [mem 0x00000000bc7b7000-0x00000000bc80efff] reserved +[ 0.000000] BIOS-e820: [mem 0x00000000bc80f000-0x00000000bc8c6fff] usable +[ 0.000000] BIOS-e820: [mem 0x00000000bc8c7000-0x00000000bc8d1fff] ACPI NVS +[ 0.000000] BIOS-e820: [mem 0x00000000bc8d2000-0x00000000bc8d4fff] ACPI data +[ 0.000000] BIOS-e820: [mem 0x00000000bc8d5000-0x00000000bc8d8fff] reserved +[ 0.000000] BIOS-e820: [mem 0x00000000bc8d9000-0x00000000bc8dcfff] ACPI NVS +[ 0.000000] BIOS-e820: [mem 0x00000000bc8dd000-0x00000000bc8dffff] reserved +[ 0.000000] BIOS-e820: [mem 0x00000000bc8e0000-0x00000000bc906fff] ACPI NVS +[ 0.000000] BIOS-e820: [mem 0x00000000bc907000-0x00000000bc907fff] ACPI data +[ 0.000000] BIOS-e820: [mem 0x00000000bc908000-0x00000000bcb0efff] reserved +[ 0.000000] BIOS-e820: [mem 0x00000000bcb0f000-0x00000000bcb9efff] ACPI NVS +[ 0.000000] BIOS-e820: [mem 0x00000000bcb9f000-0x00000000bcbfefff] ACPI data +[ 0.000000] BIOS-e820: [mem 0x00000000bcbff000-0x00000000bcbfffff] usable +[ 0.000000] BIOS-e820: [mem 0x00000000bcc00000-0x00000000beffffff] reserved +[ 0.000000] BIOS-e820: [mem 0x00000000e0000000-0x00000000efffffff] reserved +[ 0.000000] BIOS-e820: [mem 0x00000000fec00000-0x00000000fec0ffff] reserved +[ 0.000000] BIOS-e820: [mem 0x00000000fed00000-0x00000000fed003ff] reserved +[ 0.000000] BIOS-e820: [mem 0x00000000fed10000-0x00000000fed13fff] reserved +[ 0.000000] BIOS-e820: [mem 0x00000000fed18000-0x00000000fed19fff] reserved +[ 0.000000] BIOS-e820: [mem 0x00000000fed1c000-0x00000000fed8ffff] reserved +[ 0.000000] BIOS-e820: [mem 0x00000000fee00000-0x00000000fee00fff] reserved +[ 0.000000] BIOS-e820: [mem 0x00000000ff800000-0x00000000ffffffff] reserved +[ 0.000000] NX (Execute Disable) protection: active +[ 0.000000] SMBIOS 2.4 present. +[ 0.000000] DMI: LENOVO 6475GE2/6475GE2, BIOS 7UET56WW (2.02 ) 01/09/2009 +[ 0.000000] e820: update [mem 0x00000000-0x00000fff] usable ==> reserved +[ 0.000000] e820: remove [mem 0x000a0000-0x000fffff] usable +[ 0.000000] No AGP bridge found +[ 0.000000] e820: last_pfn = 0xbcc00 max_arch_pfn = 0x400000000 +[ 0.000000] MTRR default type: uncachable +[ 0.000000] MTRR fixed ranges enabled: +[ 0.000000] 00000-9FFFF write-back +[ 0.000000] A0000-BFFFF uncachable +[ 0.000000] C0000-D3FFF write-protect +[ 0.000000] D4000-DBFFF uncachable +[ 0.000000] DC000-FFFFF write-protect +[ 0.000000] MTRR variable ranges enabled: +[ 0.000000] 0 base 0BD000000 mask FFF000000 uncachable +[ 0.000000] 1 base 0BE000000 mask FFE000000 uncachable +[ 0.000000] 2 base 000000000 mask F80000000 write-back +[ 0.000000] 3 base 080000000 mask FC0000000 write-back +[ 0.000000] 4 base 0BCE00000 mask FFFE00000 uncachable +[ 0.000000] 5 disabled +[ 0.000000] 6 disabled +[ 0.000000] x86 PAT enabled: cpu 0, old 0x7040600070406, new 0x7010600070106 +[ 0.000000] original variable MTRRs +[ 0.000000] reg 0, base: 3024MB, range: 16MB, type UC +[ 0.000000] reg 1, base: 3040MB, range: 32MB, type UC +[ 0.000000] reg 2, base: 0GB, range: 2GB, type WB +[ 0.000000] reg 3, base: 2GB, range: 1GB, type WB +[ 0.000000] reg 4, base: 3022MB, range: 2MB, type UC +[ 0.000000] total RAM covered: 3022M +[ 0.000000] Found optimal setting for mtrr clean up +[ 0.000000] gran_size: 64K chunk_size: 64M num_reg: 5 lose cover RAM: 0G +[ 0.000000] New variable MTRRs +[ 0.000000] reg 0, base: 0GB, range: 2GB, type WB +[ 0.000000] reg 1, base: 2GB, range: 1GB, type WB +[ 0.000000] reg 2, base: 3022MB, range: 2MB, type UC +[ 0.000000] reg 3, base: 3024MB, range: 16MB, type UC +[ 0.000000] reg 4, base: 3040MB, range: 32MB, type UC +[ 0.000000] found SMP MP-table at [mem 0x000f6570-0x000f657f] mapped at [ffff8800000f6570] +[ 0.000000] Scanning 1 areas for low memory corruption +[ 0.000000] Base memory trampoline at [ffff880000098000] 98000 size 24576 +[ 0.000000] init_memory_mapping: [mem 0x00000000-0x000fffff] +[ 0.000000] [mem 0x00000000-0x000fffff] page 4k +[ 0.000000] BRK [0x01fd9000, 0x01fd9fff] PGTABLE +[ 0.000000] BRK [0x01fda000, 0x01fdafff] PGTABLE +[ 0.000000] BRK [0x01fdb000, 0x01fdbfff] PGTABLE +[ 0.000000] init_memory_mapping: [mem 0xbc400000-0xbc5fffff] +[ 0.000000] [mem 0xbc400000-0xbc5fffff] page 2M +[ 0.000000] BRK [0x01fdc000, 0x01fdcfff] PGTABLE +[ 0.000000] init_memory_mapping: [mem 0xbc000000-0xbc3fffff] +[ 0.000000] [mem 0xbc000000-0xbc3fffff] page 2M +[ 0.000000] init_memory_mapping: [mem 0x80000000-0xbbffffff] +[ 0.000000] [mem 0x80000000-0xbbffffff] page 2M +[ 0.000000] init_memory_mapping: [mem 0x00100000-0x7fffffff] +[ 0.000000] [mem 0x00100000-0x001fffff] page 4k +[ 0.000000] [mem 0x00200000-0x7fffffff] page 2M +[ 0.000000] init_memory_mapping: [mem 0xbc600000-0xbc6a0fff] +[ 0.000000] [mem 0xbc600000-0xbc6a0fff] page 4k +[ 0.000000] BRK [0x01fdd000, 0x01fddfff] PGTABLE +[ 0.000000] init_memory_mapping: [mem 0xbc6a7000-0xbc7b6fff] +[ 0.000000] [mem 0xbc6a7000-0xbc7b6fff] page 4k +[ 0.000000] init_memory_mapping: [mem 0xbc80f000-0xbc8c6fff] +[ 0.000000] [mem 0xbc80f000-0xbc8c6fff] page 4k +[ 0.000000] BRK [0x01fde000, 0x01fdefff] PGTABLE +[ 0.000000] init_memory_mapping: [mem 0xbcbff000-0xbcbfffff] +[ 0.000000] [mem 0xbcbff000-0xbcbfffff] page 4k +[ 0.000000] RAMDISK: [mem 0x3530e000-0x3697efff] +[ 0.000000] ACPI: RSDP 00000000000f6530 000024 (v02 LENOVO) +[ 0.000000] ACPI: XSDT 00000000bcb6a5b6 000094 (v01 LENOVO TP-7U 00002020 LTP 00000000) +[ 0.000000] ACPI: FACP 00000000bcb6a700 0000F4 (v03 LENOVO TP-7U 00002020 LNVO 00000001) +[ 0.000000] ACPI: DSDT 00000000bcb6aadb 00F0B8 (v01 LENOVO TP-7U 00002020 MSFT 03000000) +[ 0.000000] ACPI: FACS 00000000bcb8e000 000040 +[ 0.000000] ACPI: SSDT 00000000bcb6a8b4 000227 (v01 LENOVO TP-7U 00002020 MSFT 03000000) +[ 0.000000] ACPI: ECDT 00000000bcb79b93 000052 (v01 LENOVO TP-7U 00002020 LNVO 00000001) +[ 0.000000] ACPI: APIC 00000000bcb79be5 000078 (v01 LENOVO TP-7U 00002020 LNVO 00000001) +[ 0.000000] ACPI: MCFG 00000000bcb79c5d 00003C (v01 LENOVO TP-7U 00002020 LNVO 00000001) +[ 0.000000] ACPI: HPET 00000000bcb79c99 000038 (v01 LENOVO TP-7U 00002020 LNVO 00000001) +[ 0.000000] ACPI: SLIC 00000000bcb79dc2 000176 (v01 LENOVO TP-7U 00002020 LTP 00000000) +[ 0.000000] ACPI: BOOT 00000000bcb79f38 000028 (v01 LENOVO TP-7U 00002020 LTP 00000001) +[ 0.000000] ACPI: ASF! 00000000bcb79f60 0000A0 (v16 LENOVO TP-7U 00002020 PTL 00000001) +[ 0.000000] ACPI: SSDT 00000000bcb8d213 00054F (v01 LENOVO TP-7U 00002020 INTL 20050513) +[ 0.000000] ACPI: TCPA 00000000bc907000 000032 (v00 00000000 00000000) +[ 0.000000] ACPI: SSDT 00000000bc8d4000 000655 (v01 PmRef CpuPm 00003000 INTL 20050624) +[ 0.000000] ACPI: SSDT 00000000bc8d3000 000274 (v01 PmRef Cpu0Tst 00003000 INTL 20050624) +[ 0.000000] ACPI: SSDT 00000000bc8d2000 000242 (v01 PmRef ApTst 00003000 INTL 20050624) +[ 0.000000] ACPI: DMI detected: Lenovo ThinkPad T400 +[ 0.000000] ACPI: Local APIC address 0xfee00000 +[ 0.000000] No NUMA configuration found +[ 0.000000] Faking a node at [mem 0x0000000000000000-0x00000000bcbfffff] +[ 0.000000] Initmem setup node 0 [mem 0x00000000-0xbcbfffff] +[ 0.000000] NODE_DATA [mem 0xbc8c1000-0xbc8c5fff] +[ 0.000000] [ffffea0000000000-ffffea0002ffffff] PMD -> [ffff8800b8c00000-ffff8800bbbfffff] on node 0 +[ 0.000000] Zone ranges: +[ 0.000000] DMA [mem 0x00001000-0x00ffffff] +[ 0.000000] DMA32 [mem 0x01000000-0xffffffff] +[ 0.000000] Normal empty +[ 0.000000] Movable zone start for each node +[ 0.000000] Early memory node ranges +[ 0.000000] node 0: [mem 0x00001000-0x0009dfff] +[ 0.000000] node 0: [mem 0x00100000-0xbc6a0fff] +[ 0.000000] node 0: [mem 0xbc6a7000-0xbc7b6fff] +[ 0.000000] node 0: [mem 0xbc80f000-0xbc8c6fff] +[ 0.000000] node 0: [mem 0xbcbff000-0xbcbfffff] +[ 0.000000] On node 0 totalpages: 772103 +[ 0.000000] DMA zone: 64 pages used for memmap +[ 0.000000] DMA zone: 21 pages reserved +[ 0.000000] DMA zone: 3997 pages, LIFO batch:0 +[ 0.000000] DMA32 zone: 12016 pages used for memmap +[ 0.000000] DMA32 zone: 768106 pages, LIFO batch:31 +[ 0.000000] ACPI: PM-Timer IO Port: 0x1008 +[ 0.000000] ACPI: Local APIC address 0xfee00000 +[ 0.000000] ACPI: LAPIC (acpi_id[0x00] lapic_id[0x00] enabled) +[ 0.000000] ACPI: LAPIC (acpi_id[0x01] lapic_id[0x01] enabled) +[ 0.000000] ACPI: LAPIC (acpi_id[0x02] lapic_id[0x02] disabled) +[ 0.000000] ACPI: LAPIC (acpi_id[0x03] lapic_id[0x03] disabled) +[ 0.000000] ACPI: LAPIC_NMI (acpi_id[0x00] high edge lint[0x1]) +[ 0.000000] ACPI: LAPIC_NMI (acpi_id[0x01] high edge lint[0x1]) +[ 0.000000] ACPI: IOAPIC (id[0x01] address[0xfec00000] gsi_base[0]) +[ 0.000000] IOAPIC[0]: apic_id 1, version 32, address 0xfec00000, GSI 0-23 +[ 0.000000] ACPI: INT_SRC_OVR (bus 0 bus_irq 0 global_irq 2 dfl dfl) +[ 0.000000] ACPI: INT_SRC_OVR (bus 0 bus_irq 9 global_irq 9 high level) +[ 0.000000] ACPI: IRQ0 used by override. +[ 0.000000] ACPI: IRQ2 used by override. +[ 0.000000] ACPI: IRQ9 used by override. +[ 0.000000] Using ACPI (MADT) for SMP configuration information +[ 0.000000] ACPI: HPET id: 0x8086a201 base: 0xfed00000 +[ 0.000000] smpboot: Allowing 4 CPUs, 2 hotplug CPUs +[ 0.000000] nr_irqs_gsi: 40 +[ 0.000000] PM: Registered nosave memory: [mem 0x0009e000-0x0009efff] +[ 0.000000] PM: Registered nosave memory: [mem 0x0009f000-0x0009ffff] +[ 0.000000] PM: Registered nosave memory: [mem 0x000a0000-0x000dbfff] +[ 0.000000] PM: Registered nosave memory: [mem 0x000dc000-0x000fffff] +[ 0.000000] PM: Registered nosave memory: [mem 0xbc6a1000-0xbc6a6fff] +[ 0.000000] PM: Registered nosave memory: [mem 0xbc7b7000-0xbc80efff] +[ 0.000000] PM: Registered nosave memory: [mem 0xbc8c7000-0xbc8d1fff] +[ 0.000000] PM: Registered nosave memory: [mem 0xbc8d2000-0xbc8d4fff] +[ 0.000000] PM: Registered nosave memory: [mem 0xbc8d5000-0xbc8d8fff] +[ 0.000000] PM: Registered nosave memory: [mem 0xbc8d9000-0xbc8dcfff] +[ 0.000000] PM: Registered nosave memory: [mem 0xbc8dd000-0xbc8dffff] +[ 0.000000] PM: Registered nosave memory: [mem 0xbc8e0000-0xbc906fff] +[ 0.000000] PM: Registered nosave memory: [mem 0xbc907000-0xbc907fff] +[ 0.000000] PM: Registered nosave memory: [mem 0xbc908000-0xbcb0efff] +[ 0.000000] PM: Registered nosave memory: [mem 0xbcb0f000-0xbcb9efff] +[ 0.000000] PM: Registered nosave memory: [mem 0xbcb9f000-0xbcbfefff] +[ 0.000000] e820: [mem 0xbf000000-0xdfffffff] available for PCI devices +[ 0.000000] Booting paravirtualized kernel on bare hardware +[ 0.000000] setup_percpu: NR_CPUS:256 nr_cpumask_bits:256 nr_cpu_ids:4 nr_node_ids:1 +[ 0.000000] PERCPU: Embedded 29 pages/cpu @ffff8800bc200000 s86848 r8192 d23744 u524288 +[ 0.000000] pcpu-alloc: s86848 r8192 d23744 u524288 alloc=1*2097152 +[ 0.000000] pcpu-alloc: [0] 0 1 2 3 +[ 0.000000] Built 1 zonelists in Node order, mobility grouping on. Total pages: 760002 +[ 0.000000] Policy zone: DMA32 +[ 0.000000] Kernel command line: BOOT_IMAGE=/boot/vmlinuz-3.13.0-39-lowlatency root=UUID=35246665-9714-42dc-8ff4-580d4cf85131 ro nomdmonddf nomdmonisw nomdmonddf nomdmonisw +[ 0.000000] PID hash table entries: 4096 (order: 3, 32768 bytes) +[ 0.000000] Checking aperture... +[ 0.000000] No AGP bridge found +[ 0.000000] Calgary: detecting Calgary via BIOS EBDA area +[ 0.000000] Calgary: Unable to locate Rio Grande table in EBDA - bailing! +[ 0.000000] Memory: 2999200K/3088412K available (7418K kernel code, 1135K rwdata, 3420K rodata, 1324K init, 1444K bss, 89212K reserved) +[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=4, Nodes=1 +[ 0.000000] Preemptible hierarchical RCU implementation. +[ 0.000000] RCU dyntick-idle grace-period acceleration is enabled. +[ 0.000000] Dump stacks of tasks blocking RCU-preempt GP. +[ 0.000000] RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=4. +[ 0.000000] Offload RCU callbacks from all CPUs +[ 0.000000] Offload RCU callbacks from CPUs: 0-3. +[ 0.000000] NR_IRQS:16640 nr_irqs:712 16 +[ 0.000000] Console: colour VGA+ 80x25 +[ 0.000000] console [tty0] enabled +[ 0.000000] allocated 12582912 bytes of page_cgroup +[ 0.000000] please try 'cgroup_disable=memory' option if you don't want memory cgroups +[ 0.000000] hpet clockevent registered +[ 0.000000] tsc: Fast TSC calibration using PIT +[ 0.000000] tsc: Detected 2260.884 MHz processor +[ 0.001004] Calibrating delay loop (skipped), value calculated using timer frequency.. 4521.76 BogoMIPS (lpj=2260884) +[ 0.001101] pid_max: default: 32768 minimum: 301 +[ 0.001183] Security Framework initialized +[ 0.002014] AppArmor: AppArmor initialized +[ 0.002061] Yama: becoming mindful. +[ 0.002519] Dentry cache hash table entries: 524288 (order: 10, 4194304 bytes) +[ 0.005045] Inode-cache hash table entries: 262144 (order: 9, 2097152 bytes) +[ 0.006304] Mount-cache hash table entries: 8192 (order: 4, 65536 bytes) +[ 0.006363] Mountpoint-cache hash table entries: 8192 (order: 4, 65536 bytes) +[ 0.006750] Initializing cgroup subsys memory +[ 0.006805] Initializing cgroup subsys devices +[ 0.006852] Initializing cgroup subsys freezer +[ 0.006900] Initializing cgroup subsys blkio +[ 0.006946] Initializing cgroup subsys bfqio +[ 0.007006] Initializing cgroup subsys perf_event +[ 0.007056] Initializing cgroup subsys hugetlb +[ 0.007125] Disabled fast string operations +[ 0.007177] CPU: Physical Processor ID: 0 +[ 0.007222] CPU: Processor Core ID: 0 +[ 0.007269] mce: CPU supports 6 MCE banks +[ 0.007321] CPU0: Thermal monitoring enabled (TM2) +[ 0.007375] Last level iTLB entries: 4KB 128, 2MB 4, 4MB 4 +[ 0.007375] Last level dTLB entries: 4KB 256, 2MB 0, 4MB 32 +[ 0.007375] tlb_flushall_shift: -1 +[ 0.007532] Freeing SMP alternatives memory: 24K (ffffffff81e68000 - ffffffff81e6e000) +[ 0.009050] ACPI: Core revision 20131115 +[ 0.016028] ACPI: All ACPI Tables successfully acquired +[ 0.017012] ftrace: allocating 28647 entries in 112 pages +[ 0.026529] ..TIMER: vector=0x30 apic1=0 pin1=2 apic2=-1 pin2=-1 +[ 0.036750] smpboot: CPU0: Intel(R) Core(TM)2 Duo CPU P8400 @ 2.26GHz (fam: 06, model: 17, stepping: 06) +[ 0.037000] Performance Events: PEBS fmt0+, 4-deep LBR, Core2 events, Intel PMU driver. +[ 0.037000] ... version: 2 +[ 0.037000] ... bit width: 40 +[ 0.037000] ... generic registers: 2 +[ 0.037000] ... value mask: 000000ffffffffff +[ 0.037000] ... max period: 000000007fffffff +[ 0.037000] ... fixed-purpose events: 3 +[ 0.037000] ... event mask: 0000000700000003 +[ 0.045070] x86: Booting SMP configuration: +[ 0.043030] Disabled fast string operations +[ 0.057121] NMI watchdog: enabled on all CPUs, permanently consumes one hw-PMU counter. +[ 0.045118] .... node #0, CPUs: #1 +[ 0.057282] x86: Booted up 1 node, 2 CPUs +[ 0.057369] smpboot: Total of 2 processors activated (9043.53 BogoMIPS) +[ 0.058135] devtmpfs: initialized +[ 0.066825] EVM: security.selinux +[ 0.066871] EVM: security.SMACK64 +[ 0.066916] EVM: security.ima +[ 0.066960] EVM: security.capability +[ 0.067031] PM: Registering ACPI NVS region [mem 0xbc8c7000-0xbc8d1fff] (45056 bytes) +[ 0.067093] PM: Registering ACPI NVS region [mem 0xbc8d9000-0xbc8dcfff] (16384 bytes) +[ 0.067154] PM: Registering ACPI NVS region [mem 0xbc8e0000-0xbc906fff] (159744 bytes) +[ 0.067216] PM: Registering ACPI NVS region [mem 0xbcb0f000-0xbcb9efff] (589824 bytes) +[ 0.068312] pinctrl core: initialized pinctrl subsystem +[ 0.068442] regulator-dummy: no parameters +[ 0.068524] RTC time: 18:49:50, date: 03/17/15 +[ 0.068613] NET: Registered protocol family 16 +[ 0.068793] cpuidle: using governor ladder +[ 0.068840] cpuidle: using governor menu +[ 0.068936] ACPI FADT declares the system doesn't support PCIe ASPM, so disable it +[ 0.068997] ACPI: bus type PCI registered +[ 0.069006] acpiphp: ACPI Hot Plug PCI Controller Driver version: 0.5 +[ 0.069120] PCI: MMCONFIG for domain 0000 [bus 00-3f] at [mem 0xe0000000-0xe3ffffff] (base 0xe0000000) +[ 0.069184] PCI: MMCONFIG at [mem 0xe0000000-0xe3ffffff] reserved in E820 +[ 0.077236] PCI: Using configuration type 1 for base access +[ 0.078230] bio: create slab <bio-0> at 0 +[ 0.078230] ACPI: Added _OSI(Module Device) +[ 0.078230] ACPI: Added _OSI(Processor Device) +[ 0.078230] ACPI: Added _OSI(3.0 _SCP Extensions) +[ 0.078230] ACPI: Added _OSI(Processor Aggregator Device) +[ 0.078275] ACPI: Added _OSI(Linux) +[ 0.080439] ACPI : EC: EC description table is found, configuring boot EC +[ 0.085553] [Firmware Bug]: ACPI: BIOS _OSI(Linux) query honored via DMI +[ 0.094201] ACPI: SSDT 00000000bc8d7c20 0002C8 (v01 PmRef Cpu0Ist 00003000 INTL 20050624) +[ 0.094729] ACPI: Dynamic OEM Table Load: +[ 0.094837] ACPI: SSDT (null) 0002C8 (v01 PmRef Cpu0Ist 00003000 INTL 20050624) +[ 0.095093] ACPI: SSDT 00000000bc8d5020 00087A (v01 PmRef Cpu0Cst 00003001 INTL 20050624) +[ 0.095644] ACPI: Dynamic OEM Table Load: +[ 0.095752] ACPI: SSDT (null) 00087A (v01 PmRef Cpu0Cst 00003001 INTL 20050624) +[ 0.099211] ACPI: SSDT 00000000bc8d6ca0 0001CF (v01 PmRef ApIst 00003000 INTL 20050624) +[ 0.100105] ACPI: Dynamic OEM Table Load: +[ 0.100213] ACPI: SSDT (null) 0001CF (v01 PmRef ApIst 00003000 INTL 20050624) +[ 0.102068] ACPI: SSDT 00000000bc8d6f20 00008D (v01 PmRef ApCst 00003000 INTL 20050624) +[ 0.102595] ACPI: Dynamic OEM Table Load: +[ 0.103046] ACPI: SSDT (null) 00008D (v01 PmRef ApCst 00003000 INTL 20050624) +[ 0.105134] ACPI: Interpreter enabled +[ 0.105185] ACPI Exception: AE_NOT_FOUND, While evaluating Sleep State [\_S1_] (20131115/hwxface-580) +[ 0.105311] ACPI Exception: AE_NOT_FOUND, While evaluating Sleep State [\_S2_] (20131115/hwxface-580) +[ 0.105447] ACPI: (supports S0 S3 S4 S5) +[ 0.105493] ACPI: Using IOAPIC for interrupt routing +[ 0.105564] PCI: Using host bridge windows from ACPI; if necessary, use "pci=nocrs" and report a bug +[ 0.106533] ACPI: ACPI Dock Station Driver: 3 docks/bays found +[ 0.116113] ACPI: Power Resource [PUBS] (on) +[ 0.121139] ACPI: PCI Interrupt Link [LNKA] (IRQs 3 4 5 6 7 9 10 *11) +[ 0.121590] ACPI: PCI Interrupt Link [LNKB] (IRQs 3 4 5 6 7 9 10 *11) +[ 0.122046] ACPI: PCI Interrupt Link [LNKC] (IRQs 3 4 5 6 7 9 10 *11) +[ 0.122494] ACPI: PCI Interrupt Link [LNKD] (IRQs 3 4 5 6 7 9 10 *11) +[ 0.122941] ACPI: PCI Interrupt Link [LNKE] (IRQs 3 4 5 6 7 9 10 *11) +[ 0.123386] ACPI: PCI Interrupt Link [LNKF] (IRQs 3 4 5 6 7 9 10 *11) +[ 0.123832] ACPI: PCI Interrupt Link [LNKG] (IRQs 3 4 5 6 7 9 10 *11) +[ 0.124293] ACPI: PCI Interrupt Link [LNKH] (IRQs 3 4 5 6 7 9 10 *11) +[ 0.124700] ACPI: PCI Root Bridge [PCI0] (domain 0000 [bus 00-ff]) +[ 0.124754] acpi PNP0A08:00: _OSC: OS supports [ExtendedConfig ASPM ClockPM Segments MSI] +[ 0.125219] acpi PNP0A08:00: _OSC: OS now controls [PCIeHotplug PME AER PCIeCapability] +[ 0.125311] acpi PNP0A08:00: [Firmware Info]: MMCONFIG for domain 0000 [bus 00-3f] only partially covers this bridge +[ 0.125558] PCI host bridge to bus 0000:00 +[ 0.125606] pci_bus 0000:00: root bus resource [bus 00-ff] +[ 0.125655] pci_bus 0000:00: root bus resource [io 0x0000-0x0cf7] +[ 0.125705] pci_bus 0000:00: root bus resource [io 0x0d00-0xffff] +[ 0.125754] pci_bus 0000:00: root bus resource [mem 0x000a0000-0x000bffff] +[ 0.125804] pci_bus 0000:00: root bus resource [mem 0x000d4000-0x000d7fff] +[ 0.125855] pci_bus 0000:00: root bus resource [mem 0x000d8000-0x000dbfff] +[ 0.125905] pci_bus 0000:00: root bus resource [mem 0xbf000000-0xfebfffff] +[ 0.125962] pci 0000:00:00.0: [8086:2a40] type 00 class 0x060000 +[ 0.125982] DMAR: Forcing write-buffer flush capability +[ 0.126005] DMAR: Disabling IOMMU for graphics on this chipset +[ 0.126128] pci 0000:00:02.0: [8086:2a42] type 00 class 0x030000 +[ 0.126141] pci 0000:00:02.0: reg 0x10: [mem 0xf4400000-0xf47fffff 64bit] +[ 0.126148] pci 0000:00:02.0: reg 0x18: [mem 0xd0000000-0xdfffffff 64bit pref] +[ 0.126154] pci 0000:00:02.0: reg 0x20: [io 0x1800-0x1807] +[ 0.126239] pci 0000:00:02.1: [8086:2a43] type 00 class 0x038000 +[ 0.126250] pci 0000:00:02.1: reg 0x10: [mem 0xf4200000-0xf42fffff 64bit] +[ 0.126347] pci 0000:00:03.0: [8086:2a44] type 00 class 0x078000 +[ 0.126363] pci 0000:00:03.0: reg 0x10: [mem 0xfc226800-0xfc22680f 64bit] +[ 0.126414] pci 0000:00:03.0: PME# supported from D0 D3hot D3cold +[ 0.126483] pci 0000:00:03.2: [8086:2a46] type 00 class 0x010185 +[ 0.126497] pci 0000:00:03.2: reg 0x10: [io 0x1828-0x182f] +[ 0.126504] pci 0000:00:03.2: reg 0x14: [io 0x180c-0x180f] +[ 0.126511] pci 0000:00:03.2: reg 0x18: [io 0x1820-0x1827] +[ 0.126518] pci 0000:00:03.2: reg 0x1c: [io 0x1808-0x180b] +[ 0.126524] pci 0000:00:03.2: reg 0x20: [io 0x1810-0x181f] +[ 0.126622] pci 0000:00:03.3: [8086:2a47] type 00 class 0x070002 +[ 0.126636] pci 0000:00:03.3: reg 0x10: [io 0x1830-0x1837] +[ 0.126643] pci 0000:00:03.3: reg 0x14: [mem 0xfc024000-0xfc024fff] +[ 0.126800] pci 0000:00:19.0: [8086:10f5] type 00 class 0x020000 +[ 0.126825] pci 0000:00:19.0: reg 0x10: [mem 0xfc000000-0xfc01ffff] +[ 0.126837] pci 0000:00:19.0: reg 0x14: [mem 0xfc025000-0xfc025fff] +[ 0.126848] pci 0000:00:19.0: reg 0x18: [io 0x1840-0x185f] +[ 0.126939] pci 0000:00:19.0: PME# supported from D0 D3hot D3cold +[ 0.127029] pci 0000:00:19.0: System wakeup disabled by ACPI +[ 0.127114] pci 0000:00:1a.0: [8086:2937] type 00 class 0x0c0300 +[ 0.127171] pci 0000:00:1a.0: reg 0x20: [io 0x1860-0x187f] +[ 0.127276] pci 0000:00:1a.0: System wakeup disabled by ACPI +[ 0.127361] pci 0000:00:1a.1: [8086:2938] type 00 class 0x0c0300 +[ 0.127418] pci 0000:00:1a.1: reg 0x20: [io 0x1880-0x189f] +[ 0.127537] pci 0000:00:1a.2: [8086:2939] type 00 class 0x0c0300 +[ 0.127594] pci 0000:00:1a.2: reg 0x20: [io 0x18a0-0x18bf] +[ 0.127696] pci 0000:00:1a.2: System wakeup disabled by ACPI +[ 0.127792] pci 0000:00:1a.7: [8086:293c] type 00 class 0x0c0320 +[ 0.127818] pci 0000:00:1a.7: reg 0x10: [mem 0xfc226c00-0xfc226fff] +[ 0.127930] pci 0000:00:1a.7: PME# supported from D0 D3hot D3cold +[ 0.127981] pci 0000:00:1a.7: System wakeup disabled by ACPI +[ 0.128048] pci 0000:00:1b.0: [8086:293e] type 00 class 0x040300 +[ 0.128069] pci 0000:00:1b.0: reg 0x10: [mem 0xfc020000-0xfc023fff 64bit] +[ 0.128169] pci 0000:00:1b.0: PME# supported from D0 D3hot D3cold +[ 0.128224] pci 0000:00:1b.0: System wakeup disabled by ACPI +[ 0.128310] pci 0000:00:1c.0: [8086:2940] type 01 class 0x060400 +[ 0.128414] pci 0000:00:1c.0: PME# supported from D0 D3hot D3cold +[ 0.128466] pci 0000:00:1c.0: System wakeup disabled by ACPI +[ 0.128551] pci 0000:00:1c.1: [8086:2942] type 01 class 0x060400 +[ 0.128655] pci 0000:00:1c.1: PME# supported from D0 D3hot D3cold +[ 0.128706] pci 0000:00:1c.1: System wakeup disabled by ACPI +[ 0.128794] pci 0000:00:1c.3: [8086:2946] type 01 class 0x060400 +[ 0.128898] pci 0000:00:1c.3: PME# supported from D0 D3hot D3cold +[ 0.128950] pci 0000:00:1c.3: System wakeup disabled by ACPI +[ 0.129044] pci 0000:00:1c.4: [8086:2948] type 01 class 0x060400 +[ 0.129148] pci 0000:00:1c.4: PME# supported from D0 D3hot D3cold +[ 0.129202] pci 0000:00:1c.4: System wakeup disabled by ACPI +[ 0.129292] pci 0000:00:1d.0: [8086:2934] type 00 class 0x0c0300 +[ 0.129350] pci 0000:00:1d.0: reg 0x20: [io 0x18c0-0x18df] +[ 0.129453] pci 0000:00:1d.0: System wakeup disabled by ACPI +[ 0.129538] pci 0000:00:1d.1: [8086:2935] type 00 class 0x0c0300 +[ 0.129596] pci 0000:00:1d.1: reg 0x20: [io 0x18e0-0x18ff] +[ 0.129715] pci 0000:00:1d.2: [8086:2936] type 00 class 0x0c0300 +[ 0.129772] pci 0000:00:1d.2: reg 0x20: [io 0x1c00-0x1c1f] +[ 0.129902] pci 0000:00:1d.7: [8086:293a] type 00 class 0x0c0320 +[ 0.129928] pci 0000:00:1d.7: reg 0x10: [mem 0xfc227000-0xfc2273ff] +[ 0.130077] pci 0000:00:1d.7: PME# supported from D0 D3hot D3cold +[ 0.130126] pci 0000:00:1d.7: System wakeup disabled by ACPI +[ 0.130211] pci 0000:00:1e.0: [8086:2448] type 01 class 0x060401 +[ 0.130321] pci 0000:00:1e.0: System wakeup disabled by ACPI +[ 0.130413] pci 0000:00:1f.0: [8086:2917] type 00 class 0x060100 +[ 0.130633] pci 0000:00:1f.2: [8086:2929] type 00 class 0x010601 +[ 0.130660] pci 0000:00:1f.2: reg 0x10: [io 0x1c48-0x1c4f] +[ 0.130672] pci 0000:00:1f.2: reg 0x14: [io 0x183c-0x183f] +[ 0.130683] pci 0000:00:1f.2: reg 0x18: [io 0x1c40-0x1c47] +[ 0.130694] pci 0000:00:1f.2: reg 0x1c: [io 0x1838-0x183b] +[ 0.130705] pci 0000:00:1f.2: reg 0x20: [io 0x1c20-0x1c3f] +[ 0.130717] pci 0000:00:1f.2: reg 0x24: [mem 0xfc226000-0xfc2267ff] +[ 0.130788] pci 0000:00:1f.2: PME# supported from D3hot +[ 0.130868] pci 0000:00:1f.3: [8086:2930] type 00 class 0x0c0500 +[ 0.130889] pci 0000:00:1f.3: reg 0x10: [mem 0xfc227400-0xfc2274ff 64bit] +[ 0.130919] pci 0000:00:1f.3: reg 0x20: [io 0x1c60-0x1c7f] +[ 0.131080] pci 0000:00:1c.0: PCI bridge to [bus 02] +[ 0.131240] pci 0000:03:00.0: [8086:4237] type 00 class 0x028000 +[ 0.131281] pci 0000:03:00.0: reg 0x10: [mem 0xf4300000-0xf4301fff 64bit] +[ 0.131478] pci 0000:03:00.0: PME# supported from D0 D3hot D3cold +[ 0.133022] pci 0000:00:1c.1: PCI bridge to [bus 03] +[ 0.133077] pci 0000:00:1c.1: bridge window [mem 0xf4300000-0xf43fffff] +[ 0.133160] pci 0000:00:1c.3: PCI bridge to [bus 05-0c] +[ 0.133212] pci 0000:00:1c.3: bridge window [io 0x2000-0x2fff] +[ 0.133217] pci 0000:00:1c.3: bridge window [mem 0xf8000000-0xf9ffffff] +[ 0.133224] pci 0000:00:1c.3: bridge window [mem 0xf4000000-0xf40fffff 64bit pref] +[ 0.133300] pci 0000:00:1c.4: PCI bridge to [bus 0d-14] +[ 0.133300] pci 0000:00:1c.4: bridge window [io 0x3000-0x3fff] +[ 0.133300] pci 0000:00:1c.4: bridge window [mem 0xfa000000-0xfbffffff] +[ 0.133300] pci 0000:00:1c.4: bridge window [mem 0xf4100000-0xf41fffff 64bit pref] +[ 0.133300] pci 0000:15:00.0: [1180:0476] type 02 class 0x060700 +[ 0.133300] pci 0000:15:00.0: reg 0x10: [mem 0xf4800000-0xf4800fff] +[ 0.133300] pci 0000:15:00.0: supports D1 D2 +[ 0.133300] pci 0000:15:00.0: PME# supported from D0 D1 D2 D3hot D3cold +[ 0.133300] pci 0000:15:00.1: [1180:0832] type 00 class 0x0c0010 +[ 0.133300] pci 0000:15:00.1: reg 0x10: [mem 0xf4801000-0xf48017ff] +[ 0.133370] pci 0000:15:00.1: supports D1 D2 +[ 0.133372] pci 0000:15:00.1: PME# supported from D0 D1 D2 D3hot D3cold +[ 0.133486] pci 0000:00:1e.0: PCI bridge to [bus 15-18] (subtractive decode) +[ 0.133540] pci 0000:00:1e.0: bridge window [io 0x4000-0x7fff] +[ 0.133544] pci 0000:00:1e.0: bridge window [mem 0xf4800000-0xf7ffffff] +[ 0.133552] pci 0000:00:1e.0: bridge window [mem 0xf0000000-0xf3ffffff 64bit pref] +[ 0.133554] pci 0000:00:1e.0: bridge window [io 0x0000-0x0cf7] (subtractive decode) +[ 0.133556] pci 0000:00:1e.0: bridge window [io 0x0d00-0xffff] (subtractive decode) +[ 0.133558] pci 0000:00:1e.0: bridge window [mem 0x000a0000-0x000bffff] (subtractive decode) +[ 0.133560] pci 0000:00:1e.0: bridge window [mem 0x000d4000-0x000d7fff] (subtractive decode) +[ 0.133562] pci 0000:00:1e.0: bridge window [mem 0x000d8000-0x000dbfff] (subtractive decode) +[ 0.133564] pci 0000:00:1e.0: bridge window [mem 0xbf000000-0xfebfffff] (subtractive decode) +[ 0.133617] pci_bus 0000:16: busn_res: can not insert [bus 16-ff] under [bus 15-18] (conflicts with (null) [bus 15-18]) +[ 0.133622] pci_bus 0000:16: busn_res: [bus 16-ff] end is updated to 17 +[ 0.133662] acpi PNP0A08:00: Disabling ASPM (FADT indicates it is unsupported) +[ 0.135513] ACPI: Enabled 3 GPEs in block 00 to 3F +[ 0.136014] ACPI: \_SB_.PCI0: notify handler is installed +[ 0.136055] Found 1 acpi root devices +[ 0.136128] ACPI : EC: GPE = 0x11, I/O: command/status = 0x66, data = 0x62 +[ 0.136258] vgaarb: device added: PCI:0000:00:02.0,decodes=io+mem,owns=io+mem,locks=none +[ 0.136258] vgaarb: loaded +[ 0.136258] vgaarb: bridge control possible 0000:00:02.0 +[ 0.136373] SCSI subsystem initialized +[ 0.136451] libata version 3.00 loaded. +[ 0.136451] ACPI: bus type USB registered +[ 0.136451] usbcore: registered new interface driver usbfs +[ 0.136451] usbcore: registered new interface driver hub +[ 0.136451] usbcore: registered new device driver usb +[ 0.137057] PCI: Using ACPI for IRQ routing +[ 0.139507] PCI: pci_cache_line_size set to 64 bytes +[ 0.139595] e820: reserve RAM buffer [mem 0x0009ec00-0x0009ffff] +[ 0.139597] e820: reserve RAM buffer [mem 0xbc6a1000-0xbfffffff] +[ 0.139599] e820: reserve RAM buffer [mem 0xbc7b7000-0xbfffffff] +[ 0.139602] e820: reserve RAM buffer [mem 0xbc8c7000-0xbfffffff] +[ 0.139604] e820: reserve RAM buffer [mem 0xbcc00000-0xbfffffff] +[ 0.139695] NetLabel: Initializing +[ 0.139741] NetLabel: domain hash size = 128 +[ 0.139787] NetLabel: protocols = UNLABELED CIPSOv4 +[ 0.139845] NetLabel: unlabeled traffic allowed by default +[ 0.139909] HPET: 4 timers in total, 0 timers will be used for per-cpu timer +[ 0.140009] hpet0: at MMIO 0xfed00000, IRQs 2, 8, 0, 0 +[ 0.140210] hpet0: 4 comparators, 64-bit 14.318180 MHz counter +[ 0.142035] Switched to clocksource hpet +[ 0.148707] AppArmor: AppArmor Filesystem Enabled +[ 0.148799] pnp: PnP ACPI init +[ 0.148860] ACPI: bus type PNP registered +[ 0.169274] system 00:00: [mem 0x00000000-0x0009ffff] could not be reserved +[ 0.169326] system 00:00: [mem 0x000c0000-0x000c3fff] could not be reserved +[ 0.169377] system 00:00: [mem 0x000c4000-0x000c7fff] could not be reserved +[ 0.169428] system 00:00: [mem 0x000c8000-0x000cbfff] has been reserved +[ 0.169478] system 00:00: [mem 0x000cc000-0x000cffff] has been reserved +[ 0.169529] system 00:00: [mem 0x000d0000-0x000d3fff] could not be reserved +[ 0.169580] system 00:00: [mem 0x000dc000-0x000dffff] could not be reserved +[ 0.169630] system 00:00: [mem 0x000e0000-0x000e3fff] could not be reserved +[ 0.169681] system 00:00: [mem 0x000e4000-0x000e7fff] could not be reserved +[ 0.169732] system 00:00: [mem 0x000e8000-0x000ebfff] could not be reserved +[ 0.169782] system 00:00: [mem 0x000ec000-0x000effff] could not be reserved +[ 0.169833] system 00:00: [mem 0x000f0000-0x000fffff] could not be reserved +[ 0.169884] system 00:00: [mem 0x00100000-0xbeffffff] could not be reserved +[ 0.169935] system 00:00: [mem 0xfec00000-0xfed3ffff] could not be reserved +[ 0.169986] system 00:00: [mem 0xfed4c000-0xffffffff] could not be reserved +[ 0.170051] system 00:00: Plug and Play ACPI device, IDs PNP0c01 (active) +[ 0.190033] system 00:01: [io 0x164e-0x164f] has been reserved +[ 0.190084] system 00:01: [io 0x1000-0x107f] could not be reserved +[ 0.190134] system 00:01: [io 0x1180-0x11ff] has been reserved +[ 0.190184] system 00:01: [io 0x0800-0x080f] has been reserved +[ 0.190234] system 00:01: [io 0x15e0-0x15ef] has been reserved +[ 0.190283] system 00:01: [io 0x1600-0x1641] has been reserved +[ 0.190332] system 00:01: [io 0x1600-0x161b] has been reserved +[ 0.190382] system 00:01: [mem 0xe0000000-0xefffffff] has been reserved +[ 0.190433] system 00:01: [mem 0xfed1c000-0xfed1ffff] has been reserved +[ 0.191031] system 00:01: [mem 0xfed10000-0xfed13fff] has been reserved +[ 0.191082] system 00:01: [mem 0xfed18000-0xfed18fff] has been reserved +[ 0.191132] system 00:01: [mem 0xfed19000-0xfed19fff] has been reserved +[ 0.191183] system 00:01: [mem 0xfed45000-0xfed4bfff] has been reserved +[ 0.191234] system 00:01: Plug and Play ACPI device, IDs PNP0c02 (active) +[ 0.191289] pnp 00:02: Plug and Play ACPI device, IDs PNP0103 (active) +[ 0.191299] pnp 00:03: [dma 4] +[ 0.191320] pnp 00:03: Plug and Play ACPI device, IDs PNP0200 (active) +[ 0.191345] pnp 00:04: Plug and Play ACPI device, IDs PNP0800 (active) +[ 0.191385] pnp 00:05: Plug and Play ACPI device, IDs PNP0c04 (active) +[ 0.191415] pnp 00:06: Plug and Play ACPI device, IDs PNP0b00 (active) +[ 0.191447] pnp 00:07: Plug and Play ACPI device, IDs PNP0303 (active) +[ 0.191477] pnp 00:08: Plug and Play ACPI device, IDs IBM0057 PNP0f13 (active) +[ 0.211407] pnp 00:09: Plug and Play ACPI device, IDs PNP0c31 (active) +[ 0.211859] pnp: PnP ACPI: found 10 devices +[ 0.211906] ACPI: bus type PNP unregistered +[ 0.218816] pci 0000:00:1c.0: bridge window [io 0x1000-0x0fff] to [bus 02] add_size 1000 +[ 0.218820] pci 0000:00:1c.0: bridge window [mem 0x00100000-0x000fffff 64bit pref] to [bus 02] add_size 200000 +[ 0.218823] pci 0000:00:1c.0: bridge window [mem 0x00100000-0x000fffff] to [bus 02] add_size 200000 +[ 0.218834] pci 0000:00:1c.1: bridge window [io 0x1000-0x0fff] to [bus 03] add_size 1000 +[ 0.218839] pci 0000:00:1c.1: bridge window [mem 0x00100000-0x000fffff 64bit pref] to [bus 03] add_size 200000 +[ 0.218880] pci 0000:00:1c.0: res[14]=[mem 0x00100000-0x000fffff] get_res_add_size add_size 200000 +[ 0.218882] pci 0000:00:1c.0: res[15]=[mem 0x00100000-0x000fffff 64bit pref] get_res_add_size add_size 200000 +[ 0.218884] pci 0000:00:1c.1: res[15]=[mem 0x00100000-0x000fffff 64bit pref] get_res_add_size add_size 200000 +[ 0.218887] pci 0000:00:1c.0: res[13]=[io 0x1000-0x0fff] get_res_add_size add_size 1000 +[ 0.218889] pci 0000:00:1c.1: res[13]=[io 0x1000-0x0fff] get_res_add_size add_size 1000 +[ 0.218894] pci 0000:00:1c.0: BAR 14: assigned [mem 0xbf000000-0xbf1fffff] +[ 0.218946] pci 0000:00:1c.0: BAR 15: assigned [mem 0xbf200000-0xbf3fffff 64bit pref] +[ 0.219019] pci 0000:00:1c.1: BAR 15: assigned [mem 0xbf400000-0xbf5fffff 64bit pref] +[ 0.219082] pci 0000:00:1c.0: BAR 13: assigned [io 0x8000-0x8fff] +[ 0.219133] pci 0000:00:1c.1: BAR 13: assigned [io 0x9000-0x9fff] +[ 0.219184] pci 0000:00:1c.0: PCI bridge to [bus 02] +[ 0.219234] pci 0000:00:1c.0: bridge window [io 0x8000-0x8fff] +[ 0.219287] pci 0000:00:1c.0: bridge window [mem 0xbf000000-0xbf1fffff] +[ 0.219340] pci 0000:00:1c.0: bridge window [mem 0xbf200000-0xbf3fffff 64bit pref] +[ 0.219407] pci 0000:00:1c.1: PCI bridge to [bus 03] +[ 0.219456] pci 0000:00:1c.1: bridge window [io 0x9000-0x9fff] +[ 0.219509] pci 0000:00:1c.1: bridge window [mem 0xf4300000-0xf43fffff] +[ 0.219562] pci 0000:00:1c.1: bridge window [mem 0xbf400000-0xbf5fffff 64bit pref] +[ 0.219629] pci 0000:00:1c.3: PCI bridge to [bus 05-0c] +[ 0.219678] pci 0000:00:1c.3: bridge window [io 0x2000-0x2fff] +[ 0.219731] pci 0000:00:1c.3: bridge window [mem 0xf8000000-0xf9ffffff] +[ 0.219784] pci 0000:00:1c.3: bridge window [mem 0xf4000000-0xf40fffff 64bit pref] +[ 0.219850] pci 0000:00:1c.4: PCI bridge to [bus 0d-14] +[ 0.219900] pci 0000:00:1c.4: bridge window [io 0x3000-0x3fff] +[ 0.219953] pci 0000:00:1c.4: bridge window [mem 0xfa000000-0xfbffffff] +[ 0.220016] pci 0000:00:1c.4: bridge window [mem 0xf4100000-0xf41fffff 64bit pref] +[ 0.220084] pci 0000:15:00.0: res[15]=[mem 0x04000000-0x03ffffff pref] get_res_add_size add_size 4000000 +[ 0.220087] pci 0000:15:00.0: res[16]=[mem 0x04000000-0x03ffffff] get_res_add_size add_size 4000000 +[ 0.220089] pci 0000:15:00.0: res[13]=[io 0x0100-0x00ff] get_res_add_size add_size 100 +[ 0.220091] pci 0000:15:00.0: res[14]=[io 0x0100-0x00ff] get_res_add_size add_size 100 +[ 0.220094] pci 0000:15:00.0: BAR 15: assigned [mem 0xf0000000-0xf3ffffff pref] +[ 0.220156] pci 0000:15:00.0: BAR 16: assigned [mem 0xc0000000-0xc3ffffff] +[ 0.220206] pci 0000:15:00.0: BAR 13: assigned [io 0x4000-0x40ff] +[ 0.220256] pci 0000:15:00.0: BAR 14: assigned [io 0x4400-0x44ff] +[ 0.220306] pci 0000:15:00.0: CardBus bridge to [bus 16-17] +[ 0.220354] pci 0000:15:00.0: bridge window [io 0x4000-0x40ff] +[ 0.220407] pci 0000:15:00.0: bridge window [io 0x4400-0x44ff] +[ 0.220460] pci 0000:15:00.0: bridge window [mem 0xf0000000-0xf3ffffff pref] +[ 0.220524] pci 0000:15:00.0: bridge window [mem 0xc0000000-0xc3ffffff] +[ 0.220577] pci 0000:00:1e.0: PCI bridge to [bus 15-18] +[ 0.220627] pci 0000:00:1e.0: bridge window [io 0x4000-0x7fff] +[ 0.220680] pci 0000:00:1e.0: bridge window [mem 0xf4800000-0xf7ffffff] +[ 0.220733] pci 0000:00:1e.0: bridge window [mem 0xf0000000-0xf3ffffff 64bit pref] +[ 0.220800] pci_bus 0000:00: resource 4 [io 0x0000-0x0cf7] +[ 0.220802] pci_bus 0000:00: resource 5 [io 0x0d00-0xffff] +[ 0.220804] pci_bus 0000:00: resource 6 [mem 0x000a0000-0x000bffff] +[ 0.220806] pci_bus 0000:00: resource 7 [mem 0x000d4000-0x000d7fff] +[ 0.220808] pci_bus 0000:00: resource 8 [mem 0x000d8000-0x000dbfff] +[ 0.220810] pci_bus 0000:00: resource 9 [mem 0xbf000000-0xfebfffff] +[ 0.220812] pci_bus 0000:02: resource 0 [io 0x8000-0x8fff] +[ 0.220814] pci_bus 0000:02: resource 1 [mem 0xbf000000-0xbf1fffff] +[ 0.220816] pci_bus 0000:02: resource 2 [mem 0xbf200000-0xbf3fffff 64bit pref] +[ 0.220819] pci_bus 0000:03: resource 0 [io 0x9000-0x9fff] +[ 0.220821] pci_bus 0000:03: resource 1 [mem 0xf4300000-0xf43fffff] +[ 0.220823] pci_bus 0000:03: resource 2 [mem 0xbf400000-0xbf5fffff 64bit pref] +[ 0.220825] pci_bus 0000:05: resource 0 [io 0x2000-0x2fff] +[ 0.220827] pci_bus 0000:05: resource 1 [mem 0xf8000000-0xf9ffffff] +[ 0.220829] pci_bus 0000:05: resource 2 [mem 0xf4000000-0xf40fffff 64bit pref] +[ 0.220831] pci_bus 0000:0d: resource 0 [io 0x3000-0x3fff] +[ 0.220833] pci_bus 0000:0d: resource 1 [mem 0xfa000000-0xfbffffff] +[ 0.220835] pci_bus 0000:0d: resource 2 [mem 0xf4100000-0xf41fffff 64bit pref] +[ 0.220837] pci_bus 0000:15: resource 0 [io 0x4000-0x7fff] +[ 0.220839] pci_bus 0000:15: resource 1 [mem 0xf4800000-0xf7ffffff] +[ 0.220841] pci_bus 0000:15: resource 2 [mem 0xf0000000-0xf3ffffff 64bit pref] +[ 0.220843] pci_bus 0000:15: resource 4 [io 0x0000-0x0cf7] +[ 0.220845] pci_bus 0000:15: resource 5 [io 0x0d00-0xffff] +[ 0.220847] pci_bus 0000:15: resource 6 [mem 0x000a0000-0x000bffff] +[ 0.220849] pci_bus 0000:15: resource 7 [mem 0x000d4000-0x000d7fff] +[ 0.220851] pci_bus 0000:15: resource 8 [mem 0x000d8000-0x000dbfff] +[ 0.220853] pci_bus 0000:15: resource 9 [mem 0xbf000000-0xfebfffff] +[ 0.220855] pci_bus 0000:16: resource 0 [io 0x4000-0x40ff] +[ 0.220857] pci_bus 0000:16: resource 1 [io 0x4400-0x44ff] +[ 0.220859] pci_bus 0000:16: resource 2 [mem 0xf0000000-0xf3ffffff pref] +[ 0.220861] pci_bus 0000:16: resource 3 [mem 0xc0000000-0xc3ffffff] +[ 0.220895] NET: Registered protocol family 2 +[ 0.221177] TCP established hash table entries: 32768 (order: 6, 262144 bytes) +[ 0.221389] TCP bind hash table entries: 32768 (order: 7, 524288 bytes) +[ 0.221653] TCP: Hash tables configured (established 32768 bind 32768) +[ 0.221760] TCP: reno registered +[ 0.221813] UDP hash table entries: 2048 (order: 4, 65536 bytes) +[ 0.221896] UDP-Lite hash table entries: 2048 (order: 4, 65536 bytes) +[ 0.222044] NET: Registered protocol family 1 +[ 0.222105] pci 0000:00:02.0: Boot video device +[ 0.223124] PCI: CLS 64 bytes, default 64 +[ 0.223191] Trying to unpack rootfs image as initramfs... +[ 0.697471] Freeing initrd memory: 22980K (ffff88003530e000 - ffff88003697f000) +[ 0.697602] Simple Boot Flag at 0x35 set to 0x1 +[ 0.697804] microcode: CPU0 sig=0x10676, pf=0x80, revision=0x60c +[ 0.697859] microcode: CPU1 sig=0x10676, pf=0x80, revision=0x60c +[ 0.698022] microcode: Microcode Update Driver: v2.00 <tigran@aivazian.fsnet.co.uk>, Peter Oruba +[ 0.698085] Scanning for low memory corruption every 60 seconds +[ 0.698408] Initialise system trusted keyring +[ 0.698509] audit: initializing netlink socket (disabled) +[ 0.698572] type=2000 audit(1426618190.697:1): initialized +[ 0.722387] HugeTLB registered 2 MB page size, pre-allocated 0 pages +[ 0.723752] zbud: loaded +[ 0.723943] VFS: Disk quotas dquot_6.5.2 +[ 0.724046] Dquot-cache hash table entries: 512 (order 0, 4096 bytes) +[ 0.724601] fuse init (API version 7.22) +[ 0.724734] msgmni has been set to 5902 +[ 0.724842] Key type big_key registered +[ 0.725412] Key type asymmetric registered +[ 0.725461] Asymmetric key parser 'x509' registered +[ 0.725541] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 252) +[ 0.725640] io scheduler noop registered +[ 0.725689] io scheduler deadline registered +[ 0.725763] io scheduler cfq registered +[ 0.725812] io scheduler bfq registered (default) +[ 0.725859] BFQ I/O-scheduler version: v7r5 +[ 0.726126] pcieport 0000:00:1c.0: irq 40 for MSI/MSI-X +[ 0.726343] pcieport 0000:00:1c.1: irq 41 for MSI/MSI-X +[ 0.726516] pcieport 0000:00:1c.3: irq 42 for MSI/MSI-X +[ 0.726692] pcieport 0000:00:1c.4: irq 43 for MSI/MSI-X +[ 0.726843] pcieport 0000:00:1c.0: Signaling PME through PCIe PME interrupt +[ 0.726898] pcie_pme 0000:00:1c.0:pcie01: service driver pcie_pme loaded +[ 0.726954] pcieport 0000:00:1c.1: Signaling PME through PCIe PME interrupt +[ 0.727017] pci 0000:03:00.0: Signaling PME through PCIe PME interrupt +[ 0.727071] pcie_pme 0000:00:1c.1:pcie01: service driver pcie_pme loaded +[ 0.727130] pcieport 0000:00:1c.3: Signaling PME through PCIe PME interrupt +[ 0.727186] pcie_pme 0000:00:1c.3:pcie01: service driver pcie_pme loaded +[ 0.727249] pcieport 0000:00:1c.4: Signaling PME through PCIe PME interrupt +[ 0.727303] pcie_pme 0000:00:1c.4:pcie01: service driver pcie_pme loaded +[ 0.727318] pci_hotplug: PCI Hot Plug PCI Core version: 0.5 +[ 0.727424] pciehp 0000:00:1c.0:pcie04: HPC vendor_id 8086 device_id 2940 ss_vid 17aa ss_did 20f3 +[ 0.727553] pciehp 0000:00:1c.0:pcie04: service driver pciehp loaded +[ 0.727568] pciehp 0000:00:1c.1:pcie04: HPC vendor_id 8086 device_id 2942 ss_vid 17aa ss_did 20f3 +[ 0.727697] pciehp 0000:00:1c.1:pcie04: service driver pciehp loaded +[ 0.727712] pciehp 0000:00:1c.3:pcie04: HPC vendor_id 8086 device_id 2946 ss_vid 17aa ss_did 20f3 +[ 0.727840] pciehp 0000:00:1c.3:pcie04: service driver pciehp loaded +[ 0.727857] pciehp 0000:00:1c.4:pcie04: HPC vendor_id 8086 device_id 2948 ss_vid 17aa ss_did 20f3 +[ 0.727983] pciehp 0000:00:1c.4:pcie04: service driver pciehp loaded +[ 0.727992] pciehp: PCI Express Hot Plug Controller Driver version: 0.4 +[ 0.728102] intel_idle: does not run on family 6 model 23 +[ 0.728108] ipmi message handler version 39.2 +[ 0.728317] ACPI: Deprecated procfs I/F for AC is loaded, please retry with CONFIG_ACPI_PROCFS_POWER cleared +[ 0.728552] ACPI: AC Adapter [AC] (on-line) +[ 0.728689] input: Lid Switch as /devices/LNXSYSTM:00/device:00/PNP0C0D:00/input/input0 +[ 0.729044] ACPI: Lid Switch [LID] +[ 0.729128] input: Sleep Button as /devices/LNXSYSTM:00/device:00/PNP0C0E:00/input/input1 +[ 0.729192] ACPI: Sleep Button [SLPB] +[ 0.729278] input: Power Button as /devices/LNXSYSTM:00/LNXPWRBN:00/input/input2 +[ 0.729340] ACPI: Power Button [PWRF] +[ 0.730844] Monitor-Mwait will be used to enter C-1 state +[ 0.730850] Monitor-Mwait will be used to enter C-2 state +[ 0.730854] Monitor-Mwait will be used to enter C-3 state +[ 0.730857] tsc: Marking TSC unstable due to TSC halts in idle +[ 0.730914] ACPI: acpi_idle registered with cpuidle +[ 0.733365] thermal LNXTHERM:00: registered as thermal_zone0 +[ 0.733418] ACPI: Thermal Zone [THM0] (41 C) +[ 0.734886] thermal LNXTHERM:01: registered as thermal_zone1 +[ 0.734941] ACPI: Thermal Zone [THM1] (43 C) +[ 0.735032] GHES: HEST is not enabled! +[ 0.735212] ACPI: Deprecated procfs I/F for battery is loaded, please retry with CONFIG_ACPI_PROCFS_POWER cleared +[ 0.735285] ACPI: Battery Slot [BAT0] (battery absent) +[ 0.735365] Serial: 8250/16550 driver, 32 ports, IRQ sharing enabled +[ 0.757657] 0000:00:03.3: ttyS4 at I/O 0x1830 (irq = 17, base_baud = 115200) is a 16550A +[ 0.758028] Linux agpgart interface v0.103 +[ 0.758161] agpgart-intel 0000:00:00.0: Intel GM45 Chipset +[ 0.758296] agpgart-intel 0000:00:00.0: detected gtt size: 2097152K total, 262144K mappable +[ 0.759478] agpgart-intel 0000:00:00.0: detected 32768K stolen memory +[ 0.759697] agpgart-intel 0000:00:00.0: AGP aperture is 256M @ 0xd0000000 +[ 0.765051] tpm_tis 00:09: 1.2 TPM (device-id 0x1020, rev-id 6) +[ 0.765104] tpm_tis 00:09: Intel iTPM workaround enabled +[ 0.837123] tpm_tis 00:09: TPM is disabled/deactivated (0x6) +[ 0.838867] brd: module loaded +[ 0.839781] loop: module loaded +[ 0.840412] scsi0 : ata_generic +[ 0.840576] scsi1 : ata_generic +[ 0.840672] ata1: PATA max UDMA/100 cmd 0x1828 ctl 0x180c bmdma 0x1810 irq 18 +[ 0.840722] ata2: PATA max UDMA/100 cmd 0x1820 ctl 0x1808 bmdma 0x1818 irq 18 +[ 0.841130] libphy: Fixed MDIO Bus: probed +[ 0.841267] tun: Universal TUN/TAP device driver, 1.6 +[ 0.841315] tun: (C) 1999-2004 Max Krasnyansky <maxk@qualcomm.com> +[ 0.841432] PPP generic driver version 2.4.2 +[ 0.841561] ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver +[ 0.841614] ehci-pci: EHCI PCI platform driver +[ 0.841763] ehci-pci 0000:00:1a.7: EHCI Host Controller +[ 0.841816] ehci-pci 0000:00:1a.7: new USB bus registered, assigned bus number 1 +[ 0.841890] ehci-pci 0000:00:1a.7: debug port 1 +[ 0.845829] ehci-pci 0000:00:1a.7: cache line size of 64 is not supported +[ 0.845911] ehci-pci 0000:00:1a.7: irq 23, io mem 0xfc226c00 +[ 0.852066] ehci-pci 0000:00:1a.7: USB 2.0 started, EHCI 1.00 +[ 0.852201] usb usb1: New USB device found, idVendor=1d6b, idProduct=0002 +[ 0.852252] usb usb1: New USB device strings: Mfr=3, Product=2, SerialNumber=1 +[ 0.852312] usb usb1: Product: EHCI Host Controller +[ 0.852360] usb usb1: Manufacturer: Linux 3.13.0-39-lowlatency ehci_hcd +[ 0.852410] usb usb1: SerialNumber: 0000:00:1a.7 +[ 0.852583] hub 1-0:1.0: USB hub found +[ 0.852641] hub 1-0:1.0: 6 ports detected +[ 0.852924] ehci-pci 0000:00:1d.7: EHCI Host Controller +[ 0.852976] ehci-pci 0000:00:1d.7: new USB bus registered, assigned bus number 2 +[ 0.853060] ehci-pci 0000:00:1d.7: debug port 1 +[ 0.857027] ehci-pci 0000:00:1d.7: cache line size of 64 is not supported +[ 0.857110] ehci-pci 0000:00:1d.7: irq 19, io mem 0xfc227000 +[ 0.863125] ehci-pci 0000:00:1d.7: USB 2.0 started, EHCI 1.00 +[ 0.863229] usb usb2: New USB device found, idVendor=1d6b, idProduct=0002 +[ 0.863286] usb usb2: New USB device strings: Mfr=3, Product=2, SerialNumber=1 +[ 0.863347] usb usb2: Product: EHCI Host Controller +[ 0.863394] usb usb2: Manufacturer: Linux 3.13.0-39-lowlatency ehci_hcd +[ 0.863444] usb usb2: SerialNumber: 0000:00:1d.7 +[ 0.863605] hub 2-0:1.0: USB hub found +[ 0.863663] hub 2-0:1.0: 6 ports detected +[ 0.863833] ehci-platform: EHCI generic platform driver +[ 0.863889] ohci_hcd: USB 1.1 'Open' Host Controller (OHCI) Driver +[ 0.863938] ohci-pci: OHCI PCI platform driver +[ 0.863993] ohci-platform: OHCI generic platform driver +[ 0.864059] uhci_hcd: USB Universal Host Controller Interface driver +[ 0.864716] uhci_hcd 0000:00:1a.0: UHCI Host Controller +[ 0.864767] uhci_hcd 0000:00:1a.0: new USB bus registered, assigned bus number 3 +[ 0.864931] uhci_hcd 0000:00:1a.0: irq 20, io base 0x00001860 +[ 0.865045] usb usb3: New USB device found, idVendor=1d6b, idProduct=0001 +[ 0.865096] usb usb3: New USB device strings: Mfr=3, Product=2, SerialNumber=1 +[ 0.865156] usb usb3: Product: UHCI Host Controller +[ 0.865204] usb usb3: Manufacturer: Linux 3.13.0-39-lowlatency uhci_hcd +[ 0.865254] usb usb3: SerialNumber: 0000:00:1a.0 +[ 0.865419] hub 3-0:1.0: USB hub found +[ 0.865473] hub 3-0:1.0: 2 ports detected +[ 0.865668] uhci_hcd 0000:00:1a.1: UHCI Host Controller +[ 0.865720] uhci_hcd 0000:00:1a.1: new USB bus registered, assigned bus number 4 +[ 0.865881] uhci_hcd 0000:00:1a.1: irq 21, io base 0x00001880 +[ 0.865991] usb usb4: New USB device found, idVendor=1d6b, idProduct=0001 +[ 0.866063] usb usb4: New USB device strings: Mfr=3, Product=2, SerialNumber=1 +[ 0.866139] usb usb4: Product: UHCI Host Controller +[ 0.866187] usb usb4: Manufacturer: Linux 3.13.0-39-lowlatency uhci_hcd +[ 0.866243] usb usb4: SerialNumber: 0000:00:1a.1 +[ 0.866408] hub 4-0:1.0: USB hub found +[ 0.866465] hub 4-0:1.0: 2 ports detected +[ 0.866647] uhci_hcd 0000:00:1a.2: UHCI Host Controller +[ 0.866699] uhci_hcd 0000:00:1a.2: new USB bus registered, assigned bus number 5 +[ 0.866858] uhci_hcd 0000:00:1a.2: irq 22, io base 0x000018a0 +[ 0.866957] usb usb5: New USB device found, idVendor=1d6b, idProduct=0001 +[ 0.867019] usb usb5: New USB device strings: Mfr=3, Product=2, SerialNumber=1 +[ 0.867080] usb usb5: Product: UHCI Host Controller +[ 0.867128] usb usb5: Manufacturer: Linux 3.13.0-39-lowlatency uhci_hcd +[ 0.867178] usb usb5: SerialNumber: 0000:00:1a.2 +[ 0.867353] hub 5-0:1.0: USB hub found +[ 0.867407] hub 5-0:1.0: 2 ports detected +[ 0.867607] uhci_hcd 0000:00:1d.0: UHCI Host Controller +[ 0.867660] uhci_hcd 0000:00:1d.0: new USB bus registered, assigned bus number 6 +[ 0.867817] uhci_hcd 0000:00:1d.0: irq 16, io base 0x000018c0 +[ 0.867932] usb usb6: New USB device found, idVendor=1d6b, idProduct=0001 +[ 0.867983] usb usb6: New USB device strings: Mfr=3, Product=2, SerialNumber=1 +[ 0.868061] usb usb6: Product: UHCI Host Controller +[ 0.868109] usb usb6: Manufacturer: Linux 3.13.0-39-lowlatency uhci_hcd +[ 0.868158] usb usb6: SerialNumber: 0000:00:1d.0 +[ 0.868326] hub 6-0:1.0: USB hub found +[ 0.868383] hub 6-0:1.0: 2 ports detected +[ 0.868573] uhci_hcd 0000:00:1d.1: UHCI Host Controller +[ 0.868625] uhci_hcd 0000:00:1d.1: new USB bus registered, assigned bus number 7 +[ 0.868782] uhci_hcd 0000:00:1d.1: irq 17, io base 0x000018e0 +[ 0.868877] usb usb7: New USB device found, idVendor=1d6b, idProduct=0001 +[ 0.868927] usb usb7: New USB device strings: Mfr=3, Product=2, SerialNumber=1 +[ 0.868988] usb usb7: Product: UHCI Host Controller +[ 0.869050] usb usb7: Manufacturer: Linux 3.13.0-39-lowlatency uhci_hcd +[ 0.869108] usb usb7: SerialNumber: 0000:00:1d.1 +[ 0.869282] hub 7-0:1.0: USB hub found +[ 0.869339] hub 7-0:1.0: 2 ports detected +[ 0.869523] uhci_hcd 0000:00:1d.2: UHCI Host Controller +[ 0.869575] uhci_hcd 0000:00:1d.2: new USB bus registered, assigned bus number 8 +[ 0.869725] uhci_hcd 0000:00:1d.2: irq 18, io base 0x00001c00 +[ 0.869827] usb usb8: New USB device found, idVendor=1d6b, idProduct=0001 +[ 0.869878] usb usb8: New USB device strings: Mfr=3, Product=2, SerialNumber=1 +[ 0.869938] usb usb8: Product: UHCI Host Controller +[ 0.869986] usb usb8: Manufacturer: Linux 3.13.0-39-lowlatency uhci_hcd +[ 0.870048] usb usb8: SerialNumber: 0000:00:1d.2 +[ 0.870207] hub 8-0:1.0: USB hub found +[ 0.870259] hub 8-0:1.0: 2 ports detected +[ 0.870429] i8042: PNP: PS/2 Controller [PNP0303:KBD,PNP0f13:MOU] at 0x60,0x64 irq 1,12 +[ 0.878171] serio: i8042 KBD port at 0x60,0x64 irq 1 +[ 0.878246] serio: i8042 AUX port at 0x60,0x64 irq 12 +[ 0.878429] mousedev: PS/2 mouse device common for all mice +[ 0.878688] rtc_cmos 00:06: RTC can wake from S4 +[ 0.878876] rtc_cmos 00:06: rtc core: registered rtc_cmos as rtc0 +[ 0.878999] rtc_cmos 00:06: alarms up to one month, y3k, 114 bytes nvram, hpet irqs +[ 0.879154] device-mapper: uevent: version 1.0.3 +[ 0.879274] device-mapper: ioctl: 4.27.0-ioctl (2013-10-30) initialised: dm-devel@redhat.com +[ 0.879342] ledtrig-cpu: registered to indicate activity on CPUs +[ 0.879495] TCP: cubic registered +[ 0.879638] NET: Registered protocol family 10 +[ 0.879887] NET: Registered protocol family 17 +[ 0.879946] Key type dns_resolver registered +[ 0.880318] Loading compiled-in X.509 certificates +[ 0.881536] Loaded X.509 cert 'Magrathea: Glacier signing key: a7171335f18ca6131c1947ca87d46fb662317fa6' +[ 0.881611] registered taskstats version 1 +[ 0.883655] input: AT Translated Set 2 keyboard as /devices/platform/i8042/serio0/input/input3 +[ 0.884186] Key type trusted registered +[ 0.886362] Key type encrypted registered +[ 0.888541] AppArmor: AppArmor sha1 policy hashing enabled +[ 0.906069] tpm_tis 00:09: A TPM error (6) occurred attempting to read a pcr value +[ 0.906134] IMA: No TPM chip found, activating TPM-bypass! +[ 0.906542] regulator-dummy: disabling +[ 0.906622] Magic number: 7:954:847 +[ 0.906816] rtc_cmos 00:06: setting system clock to 2015-03-17 18:49:51 UTC (1426618191) +[ 0.909146] BIOS EDD facility v0.16 2004-Jun-25, 0 devices found +[ 0.909198] EDD information not available. +[ 0.909325] PM: Hibernation image not present or could not be loaded. +[ 1.164738] Freeing unused kernel memory: 1324K (ffffffff81d1d000 - ffffffff81e68000) +[ 1.164804] Write protecting the kernel read-only data: 12288k +[ 1.168375] Freeing unused kernel memory: 764K (ffff880001741000 - ffff880001800000) +[ 1.171458] Freeing unused kernel memory: 676K (ffff880001b57000 - ffff880001c00000) +[ 1.191531] systemd-udevd[133]: starting version 204 +[ 1.220543] pps_core: LinuxPPS API ver. 1 registered +[ 1.220600] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it> +[ 1.225352] PTP clock support registered +[ 1.236203] e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k +[ 1.236368] e1000e: Copyright(c) 1999 - 2013 Intel Corporation. +[ 1.236654] e1000e 0000:00:19.0: Interrupt Throttling Rate (ints/sec) set to dynamic conservative mode +[ 1.236749] e1000e 0000:00:19.0: irq 44 for MSI/MSI-X +[ 1.245390] wmi: Mapper loaded +[ 1.246806] [drm] Initialized drm 1.1.0 20060810 +[ 1.353201] firewire_ohci 0000:15:00.1: added OHCI v1.10 device as card 0, 4 IR + 4 IT contexts, quirks 0x11 +[ 1.446329] e1000e 0000:00:19.0 eth0: (PCI Express:2.5GT/s:Width x1) 00:1c:25:9f:c6:0e +[ 1.446396] e1000e 0000:00:19.0 eth0: Intel(R) PRO/1000 Network Connection +[ 1.446475] e1000e 0000:00:19.0 eth0: MAC: 7, PHY: 8, PBA No: 1008FF-0FF +[ 1.446570] ahci 0000:00:1f.2: version 3.0 +[ 1.446766] ahci 0000:00:1f.2: irq 45 for MSI/MSI-X +[ 1.446816] ahci 0000:00:1f.2: SSS flag set, parallel bus scan disabled +[ 1.446896] ahci 0000:00:1f.2: AHCI 0001.0200 32 slots 4 ports 3 Gbps 0x3 impl SATA mode +[ 1.446962] ahci 0000:00:1f.2: flags: 64bit ncq sntf stag pm led clo pio slum part ccc sxs +[ 1.448104] scsi2 : ahci +[ 1.448255] scsi3 : ahci +[ 1.448399] scsi4 : ahci +[ 1.448552] scsi5 : ahci +[ 1.448664] ata3: SATA max UDMA/133 abar m2048@0xfc226000 port 0xfc226100 irq 45 +[ 1.448734] ata4: SATA max UDMA/133 abar m2048@0xfc226000 port 0xfc226180 irq 45 +[ 1.448797] ata5: DUMMY +[ 1.448843] ata6: DUMMY +[ 1.449570] [drm] Memory usable by graphics device = 2048M +[ 1.510078] usb 4-2: new full-speed USB device number 2 using uhci_hcd +[ 1.514075] i915 0000:00:02.0: irq 46 for MSI/MSI-X +[ 1.514086] [drm] Supports vblank timestamp caching Rev 2 (21.10.2013). +[ 1.514139] [drm] Driver supports precise vblank timestamp query. +[ 1.514341] vgaarb: device changed decodes: PCI:0000:00:02.0,olddecodes=io+mem,decodes=io+mem:owns=io+mem +[ 1.630078] [drm] GMBUS [i915 gmbus dpb] timed out, falling back to bit banging on pin 5 +[ 1.665898] fbcon: inteldrmfb (fb0) is primary device +[ 1.667027] usb 4-2: New USB device found, idVendor=0a5c, idProduct=2145 +[ 1.667030] usb 4-2: New USB device strings: Mfr=1, Product=2, SerialNumber=0 +[ 1.667032] usb 4-2: Product: ThinkPad Bluetooth with Enhanced Data Rate II +[ 1.667033] usb 4-2: Manufacturer: Lenovo Computer Corp +[ 1.755095] ata3: SATA link up 1.5 Gbps (SStatus 113 SControl 300) +[ 1.756251] ata3.00: ACPI cmd ef/02:00:00:00:00:a0 (SET FEATURES) succeeded +[ 1.756253] ata3.00: ACPI cmd f5/00:00:00:00:00:a0 (SECURITY FREEZE LOCK) filtered out +[ 1.756362] ata3.00: ACPI cmd ef/5f:00:00:00:00:a0 (SET FEATURES) succeeded +[ 1.756364] ata3.00: ACPI cmd ef/10:03:00:00:00:a0 (SET FEATURES) filtered out +[ 1.809909] ata3.00: ATA-8: WDC WD1600BEVS-08VAT1, 13.01A13, max UDMA/133 +[ 1.809911] ata3.00: 312581808 sectors, multi 16: LBA48 NCQ (depth 31/32), AA +[ 1.811456] ata3.00: ACPI cmd ef/02:00:00:00:00:a0 (SET FEATURES) succeeded +[ 1.811459] ata3.00: ACPI cmd f5/00:00:00:00:00:a0 (SECURITY FREEZE LOCK) filtered out +[ 1.811639] ata3.00: ACPI cmd ef/5f:00:00:00:00:a0 (SET FEATURES) succeeded +[ 1.811642] ata3.00: ACPI cmd ef/10:03:00:00:00:a0 (SET FEATURES) filtered out +[ 1.813118] ata3.00: configured for UDMA/133 +[ 1.813311] scsi 2:0:0:0: Direct-Access ATA WDC WD1600BEVS-0 13.0 PQ: 0 ANSI: 5 +[ 1.813543] sd 2:0:0:0: Attached scsi generic sg0 type 0 +[ 1.813561] sd 2:0:0:0: [sda] 312581808 512-byte logical blocks: (160 GB/149 GiB) +[ 1.813724] sd 2:0:0:0: [sda] Write Protect is off +[ 1.813726] sd 2:0:0:0: [sda] Mode Sense: 00 3a 00 00 +[ 1.813787] sd 2:0:0:0: [sda] Write cache: enabled, read cache: enabled, doesn't support DPO or FUA +[ 1.848656] sda: sda1 sda2 < sda5 sda6 > +[ 1.849262] sd 2:0:0:0: [sda] Attached SCSI disk +[ 1.854171] firewire_core 0000:15:00.1: created device fw0: GUID 00016c2000a28887, S400 +[ 2.051419] psmouse serio1: synaptics: Touchpad model: 1, fw: 7.0, id: 0x1c0b1, caps: 0xd04791/0xb00000/0x20000, board id: 71, fw id: 434116 +[ 2.051428] psmouse serio1: synaptics: serio: Synaptics pass-through port at isa0060/serio1/input0 +[ 2.091571] input: SynPS/2 Synaptics TouchPad as /devices/platform/i8042/serio1/input/input5 +[ 2.118180] ata4: SATA link up 1.5 Gbps (SStatus 113 SControl 300) +[ 2.121457] ata4.00: ACPI cmd e3/00:1f:00:00:00:a0 (IDLE) succeeded +[ 2.122567] ata4.00: ACPI cmd e3/00:02:00:00:00:a0 (IDLE) succeeded +[ 2.124134] ata4.00: ATAPI: HL-DT-STCD-RW/DVD DRIVE MU10N, 1.05, max UDMA/33 +[ 2.128528] ata4.00: ACPI cmd e3/00:1f:00:00:00:a0 (IDLE) succeeded +[ 2.129580] ata4.00: ACPI cmd e3/00:02:00:00:00:a0 (IDLE) succeeded +[ 2.131137] ata4.00: configured for UDMA/33 +[ 2.140042] scsi 3:0:0:0: CD-ROM HL-DT-ST RW/DVD MU10N 1.05 PQ: 0 ANSI: 5 +[ 2.145419] sr0: scsi3-mmc drive: 24x/24x writer cd/rw xa/form2 cdda tray +[ 2.145420] cdrom: Uniform CD-ROM driver Revision: 3.20 +[ 2.145549] sr 3:0:0:0: Attached scsi CD-ROM sr0 +[ 2.145741] sr 3:0:0:0: Attached scsi generic sg1 type 5 +[ 2.208787] Console: switching to colour frame buffer device 160x50 +[ 2.227499] i915 0000:00:02.0: fb0: inteldrmfb frame buffer device +[ 2.229383] i915 0000:00:02.0: registered panic notifier +[ 2.234366] ACPI: Video Device [VID] (multi-head: yes rom: no post: no) +[ 2.243759] acpi device:02: registered as cooling_device2 +[ 2.245794] input: Video Bus as /devices/LNXSYSTM:00/device:00/PNP0A08:00/LNXVIDEO:00/input/input7 +[ 2.247868] [drm] Initialized i915 1.6.0 20080730 for 0000:00:02.0 on minor 0 +[ 2.578407] random: nonblocking pool is initialized +[ 2.822478] md: linear personality registered for level -1 +[ 2.826736] md: multipath personality registered for level -4 +[ 2.831280] md: raid0 personality registered for level 0 +[ 2.836263] md: raid1 personality registered for level 1 +[ 2.858032] raid6: sse2x1 2871 MB/s +[ 2.875030] raid6: sse2x2 3324 MB/s +[ 2.892030] raid6: sse2x4 4656 MB/s +[ 2.892057] raid6: using algorithm sse2x4 (4656 MB/s) +[ 2.892090] raid6: using ssse3x2 recovery algorithm +[ 2.894557] xor: measuring software checksum speed +[ 2.904030] prefetch64-sse: 6452.000 MB/sec +[ 2.914030] generic_sse: 5740.000 MB/sec +[ 2.914061] xor: using function: prefetch64-sse (6452.000 MB/sec) +[ 2.916259] async_tx: api initialized (async) +[ 2.928184] md: raid6 personality registered for level 6 +[ 2.928222] md: raid5 personality registered for level 5 +[ 2.928257] md: raid4 personality registered for level 4 +[ 2.937068] md: raid10 personality registered for level 10 +[ 3.093997] bio: create slab <bio-1> at 1 +[ 3.094936] Btrfs loaded +[ 3.390369] EXT4-fs (sda1): mounted filesystem with ordered data mode. Opts: (null) +[ 5.358449] psmouse serio2: alps: Unknown ALPS touchpad: E7=10 00 64, EC=10 00 64 +[ 5.988517] Adding 4230140k swap on /dev/sda5. Priority:-1 extents:1 across:4230140k FS +[ 6.808061] psmouse serio2: trackpoint: IBM TrackPoint firmware: 0x0e, buttons: 3/3 +[ 7.040928] input: TPPS/2 IBM TrackPoint as /devices/platform/i8042/serio1/serio2/input/input6 +[ 7.402514] IPv6: ADDRCONF(NETDEV_UP): eth0: link is not ready +[ 7.640430] EXT4-fs (sda1): re-mounted. Opts: errors=remount-ro +[ 7.641692] systemd-udevd[425]: starting version 204 +[ 8.377312] lp: driver loaded but no devices found +[ 8.451574] ppdev: user-space parallel port driver +[ 8.663285] SGI XFS with ACLs, security attributes, realtime, large block/inode numbers, no debug enabled +[ 8.763636] XFS (sda6): Mounting Filesystem +[ 8.987137] XFS (sda6): Ending clean mount +[ 9.764969] cfg80211: Calling CRDA to update world regulatory domain +[ 9.815431] Intel(R) Wireless WiFi driver for Linux, in-tree: +[ 9.815435] Copyright(c) 2003-2013 Intel Corporation +[ 9.815585] iwlwifi 0000:03:00.0: can't disable ASPM; OS doesn't have ASPM control +[ 9.815653] iwlwifi 0000:03:00.0: irq 47 for MSI/MSI-X +[ 9.815784] 0000:03:00.0: Missing Free firmware +[ 9.817262] iwlwifi 0000:03:00.0: Couldn't request the fw +[ 9.818920] iwlwifi: probe of 0000:03:00.0 failed with error -22 +[ 10.041861] pci 0000:03:00.0: Direct firmware load failed with error -2 +[ 10.041867] pci 0000:03:00.0: Falling back to user helper +[ 10.115482] ACPI Warning: 0x0000000000001028-0x000000000000102f SystemIO conflicts with Region \_SB_.PCI0.LPC_.PMIO 1 (20131115/utaddress-251) +[ 10.115492] ACPI: If an ACPI driver is available for this device, you should use it instead of the native driver +[ 10.115497] ACPI Warning: 0x00000000000011b0-0x00000000000011bf SystemIO conflicts with Region \_SB_.PCI0.LPC_.LPIO 1 (20131115/utaddress-251) +[ 10.115501] ACPI: If an ACPI driver is available for this device, you should use it instead of the native driver +[ 10.115503] ACPI Warning: 0x0000000000001180-0x00000000000011af SystemIO conflicts with Region \_SB_.PCI0.LPC_.LPIO 1 (20131115/utaddress-251) +[ 10.115508] ACPI: If an ACPI driver is available for this device, you should use it instead of the native driver +[ 10.115510] lpc_ich: Resource conflict(s) found affecting gpio_ich +[ 10.261508] yenta_cardbus 0000:15:00.0: CardBus bridge found [17aa:20c6] +[ 10.383852] yenta_cardbus 0000:15:00.0: ISA IRQ mask 0x04b8, PCI irq 16 +[ 10.383859] yenta_cardbus 0000:15:00.0: Socket status: 30000006 +[ 10.383867] yenta_cardbus 0000:15:00.0: pcmcia: parent PCI bridge window: [io 0x4000-0x7fff] +[ 10.383870] yenta_cardbus 0000:15:00.0: pcmcia: parent PCI bridge window: [mem 0xf4800000-0xf7ffffff] +[ 10.383874] pcmcia_socket pcmcia_socket0: cs: memory probe 0xf4800000-0xf7ffffff: +[ 10.383879] excluding 0xf4800000-0xf4b7ffff +[ 10.383891] yenta_cardbus 0000:15:00.0: pcmcia: parent PCI bridge window: [mem 0xf0000000-0xf3ffffff 64bit pref] +[ 10.383894] pcmcia_socket pcmcia_socket0: cs: memory probe 0xf0000000-0xf3ffffff: +[ 10.383906] excluding 0xf0000000-0xf3ffffff +[ 10.625496] device-mapper: multipath: version 1.6.0 loaded +[ 10.870142] mei_me 0000:00:03.0: irq 47 for MSI/MSI-X +[ 10.907864] Non-volatile memory driver v1.3 +[ 10.975070] thinkpad_acpi: ThinkPad ACPI Extras v0.25 +[ 10.975074] thinkpad_acpi: http://ibm-acpi.sf.net/ +[ 10.975076] thinkpad_acpi: ThinkPad BIOS 7UET56WW (2.02 ), EC 7VHT12WW-1.01 +[ 10.975078] thinkpad_acpi: Lenovo ThinkPad T400, model 6475GE2 +[ 11.003621] thinkpad_acpi: detected a 16-level brightness capable ThinkPad +[ 11.003835] thinkpad_acpi: radio switch found; radios are enabled +[ 11.003857] thinkpad_acpi: This ThinkPad has standard ACPI backlight brightness control, supported by the ACPI video driver +[ 11.003859] thinkpad_acpi: Disabling thinkpad-acpi brightness events by default... +[ 11.008052] thinkpad_acpi: rfkill switch tpacpi_bluetooth_sw: radio is unblocked +[ 11.014406] thinkpad_acpi: Standard ACPI backlight interface available, not loading native one +[ 11.014610] thinkpad_acpi: Console audio control enabled, mode: monitor (read only) +[ 11.018306] input: ThinkPad Extra Buttons as /devices/platform/thinkpad_acpi/input/input8 +[ 11.199291] kvm: disabled by bios +[ 11.205924] kvm: disabled by bios +[ 12.346341] init: avahi-cups-reload main process (668) terminated with status 1 +[ 12.979286] type=1400 audit(1426618203.572:2): apparmor="STATUS" operation="profile_load" profile="unconfined" name="/sbin/dhclient" pid=602 comm="apparmor_parser" +[ 12.979296] type=1400 audit(1426618203.572:3): apparmor="STATUS" operation="profile_load" profile="unconfined" name="/usr/lib/NetworkManager/nm-dhcp-client.action" pid=602 comm="apparmor_parser" +[ 12.979303] type=1400 audit(1426618203.572:4): apparmor="STATUS" operation="profile_load" profile="unconfined" name="/usr/lib/connman/scripts/dhclient-script" pid=602 comm="apparmor_parser" +[ 12.979315] type=1400 audit(1426618203.572:5): apparmor="STATUS" operation="profile_replace" profile="unconfined" name="/sbin/dhclient" pid=532 comm="apparmor_parser" +[ 12.979324] type=1400 audit(1426618203.572:6): apparmor="STATUS" operation="profile_replace" profile="unconfined" name="/usr/lib/NetworkManager/nm-dhcp-client.action" pid=532 comm="apparmor_parser" +[ 12.979331] type=1400 audit(1426618203.572:7): apparmor="STATUS" operation="profile_replace" profile="unconfined" name="/usr/lib/connman/scripts/dhclient-script" pid=532 comm="apparmor_parser" +[ 12.979954] type=1400 audit(1426618203.572:8): apparmor="STATUS" operation="profile_replace" profile="unconfined" name="/usr/lib/NetworkManager/nm-dhcp-client.action" pid=602 comm="apparmor_parser" +[ 12.979961] type=1400 audit(1426618203.572:9): apparmor="STATUS" operation="profile_replace" profile="unconfined" name="/usr/lib/connman/scripts/dhclient-script" pid=602 comm="apparmor_parser" +[ 12.979981] type=1400 audit(1426618203.572:10): apparmor="STATUS" operation="profile_replace" profile="unconfined" name="/usr/lib/NetworkManager/nm-dhcp-client.action" pid=532 comm="apparmor_parser" +[ 12.979988] type=1400 audit(1426618203.572:11): apparmor="STATUS" operation="profile_replace" profile="unconfined" name="/usr/lib/connman/scripts/dhclient-script" pid=532 comm="apparmor_parser" +[ 12.996307] pcmcia_socket pcmcia_socket0: cs: memory probe 0x0c0000-0x0fffff: +[ 12.996318] excluding 0xc0000-0xd3fff 0xdc000-0xfffff +[ 12.996348] pcmcia_socket pcmcia_socket0: cs: memory probe 0xa0000000-0xa0ffffff: +[ 12.996358] excluding 0xa0000000-0xa0ffffff +[ 12.996381] pcmcia_socket pcmcia_socket0: cs: memory probe 0x60000000-0x60ffffff: +[ 12.996390] excluding 0x60000000-0x60ffffff +[ 14.072556] Bluetooth: Core ver 2.17 +[ 14.072608] NET: Registered protocol family 31 +[ 14.072611] Bluetooth: HCI device and connection manager initialized +[ 14.072623] Bluetooth: HCI socket layer initialized +[ 14.072627] Bluetooth: L2CAP socket layer initialized +[ 14.072633] Bluetooth: SCO socket layer initialized +[ 14.168500] Bluetooth: BNEP (Ethernet Emulation) ver 1.3 +[ 14.168506] Bluetooth: BNEP filters: protocol multicast +[ 14.168518] Bluetooth: BNEP socket layer initialized +[ 14.169341] Bluetooth: RFCOMM TTY layer initialized +[ 14.169352] Bluetooth: RFCOMM socket layer initialized +[ 14.169361] Bluetooth: RFCOMM ver 1.11 +[ 14.178064] snd_hda_intel 0000:00:1b.0: irq 48 for MSI/MSI-X +[ 14.229289] hda_codec: CX20561 (Hermosa): BIOS auto-probing. +[ 14.229771] autoconfig: line_outs=1 (0x1a/0x0/0x0/0x0/0x0) type:speaker +[ 14.229774] speaker_outs=0 (0x0/0x0/0x0/0x0/0x0) +[ 14.229776] hp_outs=2 (0x19/0x16/0x0/0x0/0x0) +[ 14.229778] mono: mono_out=0x0 +[ 14.229779] dig-out=0x1c/0x0 +[ 14.229781] inputs: +[ 14.229783] Mic=0x18 +[ 14.229785] Internal Mic=0x1d +[ 14.229787] Dock Mic=0x17 +[ 14.230909] hda_codec: Enable sync_write for stable communication +[ 14.234697] input: HDA Intel Headphone as /devices/pci0000:00/0000:00:1b.0/sound/card0/input12 +[ 14.234908] input: HDA Intel Dock Headphone as /devices/pci0000:00/0000:00:1b.0/sound/card0/input11 +[ 14.235118] input: HDA Intel Dock Mic as /devices/pci0000:00/0000:00:1b.0/sound/card0/input10 +[ 14.235298] input: HDA Intel Mic as /devices/pci0000:00/0000:00:1b.0/sound/card0/input9 +[ 14.294724] init: failsafe main process (699) killed by TERM signal +[ 14.300364] usbcore: registered new interface driver btusb +[ 15.826334] e1000e 0000:00:19.0: irq 44 for MSI/MSI-X +[ 15.927162] e1000e 0000:00:19.0: irq 44 for MSI/MSI-X +[ 15.927347] IPv6: ADDRCONF(NETDEV_UP): eth0: link is not ready +[ 15.927754] IPv6: ADDRCONF(NETDEV_UP): eth0: link is not ready +[ 16.972911] init: alsa-restore main process (987) terminated with status 99 +[ 19.430838] init: plymouth-upstart-bridge main process ended, respawning +[ 19.613929] e1000e: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: Rx/Tx +[ 19.614080] IPv6: ADDRCONF(NETDEV_CHANGE): eth0: link becomes ready +[ 97.723392] init: upstart-udev-bridge main process (418) terminated with status 1 +[ 97.723413] init: upstart-udev-bridge main process ended, respawning +[ 97.723636] init: upstart-file-bridge main process (528) terminated with status 1 +[ 97.723652] init: upstart-file-bridge main process ended, respawning +[ 97.723833] init: upstart-socket-bridge main process (712) terminated with status 1 +[ 97.723849] init: upstart-socket-bridge main process ended, respawning +[ 477.962196] perf samples too long (2508 > 2500), lowering kernel.perf_event_max_sample_rate to 50000 +[ 681.763788] show_signal_msg: 114 callbacks suppressed +[ 681.763795] msrtool[12415]: segfault at 0 ip (null) sp 00007fff82509228 error 14 in msrtool[400000+26be000] diff --git a/docs/future/dumps/logs-t400-bios2.02-ec1.01/dmidecode.log b/docs/future/dumps/logs-t400-bios2.02-ec1.01/dmidecode.log @@ -0,0 +1,611 @@ +# dmidecode 2.12 +SMBIOS 2.4 present. +74 structures occupying 2469 bytes. +Table at 0x000E0010. + +Handle 0x0000, DMI type 0, 24 bytes +BIOS Information + Vendor: LENOVO + Version: 7UET56WW (2.02 ) + Release Date: 01/09/2009 + Address: 0xE0000 + Runtime Size: 128 kB + ROM Size: 8192 kB + Characteristics: + PCI is supported + PC Card (PCMCIA) is supported + PNP is supported + BIOS is upgradeable + BIOS shadowing is allowed + ESCD support is available + Boot from CD is supported + Selectable boot is supported + BIOS ROM is socketed + EDD is supported + ACPI is supported + USB legacy is supported + BIOS boot specification is supported + Targeted content distribution is supported + BIOS Revision: 2.2 + Firmware Revision: 1.1 + +Handle 0x0001, DMI type 1, 27 bytes +System Information + Manufacturer: LENOVO + Product Name: 6475GE2 + Version: ThinkPad T400 + Serial Number: L3BLN3R + UUID: 044E2A01-4A58-11CB-B7F3-A659D406AA70 + Wake-up Type: Power Switch + SKU Number: Not Specified + Family: ThinkPad T400 + +Handle 0x0002, DMI type 2, 8 bytes +Base Board Information + Manufacturer: LENOVO + Product Name: 6475GE2 + Version: Not Available + Serial Number: VF26F91C27K + +Handle 0x0003, DMI type 3, 13 bytes +Chassis Information + Manufacturer: LENOVO + Type: Notebook + Lock: Not Present + Version: Not Available + Serial Number: Not Available + Asset Tag: 9662148 + Boot-up State: Unknown + Power Supply State: Unknown + Thermal State: Unknown + Security Status: Unknown + +Handle 0x0004, DMI type 126, 13 bytes +Inactive + +Handle 0x0005, DMI type 126, 13 bytes +Inactive + +Handle 0x0006, DMI type 4, 35 bytes +Processor Information + Socket Designation: None + Type: Central Processor + Family: Other + Manufacturer: GenuineIntel + ID: 76 06 01 00 FF FB EB BF + Signature: Type 0, Family 6, Model 23, Stepping 6 + Flags: + FPU (Floating-point unit on-chip) + VME (Virtual mode extension) + DE (Debugging extension) + PSE (Page size extension) + TSC (Time stamp counter) + MSR (Model specific registers) + PAE (Physical address extension) + MCE (Machine check exception) + CX8 (CMPXCHG8 instruction supported) + APIC (On-chip APIC hardware supported) + SEP (Fast system call) + MTRR (Memory type range registers) + PGE (Page global enable) + MCA (Machine check architecture) + CMOV (Conditional move instruction supported) + PAT (Page attribute table) + PSE-36 (36-bit page size extension) + CLFSH (CLFLUSH instruction supported) + DS (Debug store) + ACPI (ACPI supported) + MMX (MMX technology supported) + FXSR (FXSAVE and FXSTOR instructions supported) + SSE (Streaming SIMD extensions) + SSE2 (Streaming SIMD extensions 2) + SS (Self-snoop) + HTT (Multi-threading) + TM (Thermal monitor supported) + PBE (Pending break enabled) + Version: Intel(R) Core(TM)2 Duo CPU P8400 @ 2.26GHz + Voltage: 1.2 V + External Clock: 266 MHz + Max Speed: 2260 MHz + Current Speed: 2260 MHz + Status: Populated, Enabled + Upgrade: None + L1 Cache Handle: 0x000A + L2 Cache Handle: 0x000C + L3 Cache Handle: Not Provided + Serial Number: Not Specified + Asset Tag: Not Specified + Part Number: Not Specified + +Handle 0x0007, DMI type 5, 20 bytes +Memory Controller Information + Error Detecting Method: None + Error Correcting Capabilities: + None + Supported Interleave: One-way Interleave + Current Interleave: One-way Interleave + Maximum Memory Module Size: 4096 MB + Maximum Total Memory Size: 8192 MB + Supported Speeds: + Other + Supported Memory Types: + DIMM + SDRAM + Memory Module Voltage: 2.9 V + Associated Memory Slots: 2 + 0x0008 + 0x0009 + Enabled Error Correcting Capabilities: + Unknown + +Handle 0x0008, DMI type 6, 12 bytes +Memory Module Information + Socket Designation: DIMM Slot 1 + Bank Connections: 0 1 + Current Speed: 155 ns + Type: DIMM SDRAM + Installed Size: 1024 MB (Double-bank Connection) + Enabled Size: 1024 MB (Double-bank Connection) + Error Status: OK + +Handle 0x0009, DMI type 6, 12 bytes +Memory Module Information + Socket Designation: DIMM Slot 2 + Bank Connections: 2 3 + Current Speed: 155 ns + Type: DIMM SDRAM + Installed Size: 2048 MB (Single-bank Connection) + Enabled Size: 2048 MB (Single-bank Connection) + Error Status: OK + +Handle 0x000A, DMI type 7, 19 bytes +Cache Information + Socket Designation: Internal L1 Cache + Configuration: Enabled, Socketed, Level 1 + Operational Mode: Write Back + Location: Internal + Installed Size: 64 kB + Maximum Size: 64 kB + Supported SRAM Types: + Synchronous + Installed SRAM Type: Synchronous + Speed: Unknown + Error Correction Type: Single-bit ECC + System Type: Instruction + Associativity: 8-way Set-associative + +Handle 0x000B, DMI type 7, 19 bytes +Cache Information + Socket Designation: Internal L1 Cache + Configuration: Enabled, Socketed, Level 1 + Operational Mode: Write Back + Location: Internal + Installed Size: 64 kB + Maximum Size: 64 kB + Supported SRAM Types: + Synchronous + Installed SRAM Type: Synchronous + Speed: Unknown + Error Correction Type: Single-bit ECC + System Type: Data + Associativity: 8-way Set-associative + +Handle 0x000C, DMI type 7, 19 bytes +Cache Information + Socket Designation: Internal L2 Cache + Configuration: Enabled, Socketed, Level 2 + Operational Mode: Write Back + Location: Internal + Installed Size: 3072 kB + Maximum Size: 3072 kB + Supported SRAM Types: + Burst + Installed SRAM Type: Burst + Speed: Unknown + Error Correction Type: Single-bit ECC + System Type: Unified + Associativity: 8-way Set-associative + +Handle 0x000D, DMI type 8, 9 bytes +Port Connector Information + Internal Reference Designator: Not Available + Internal Connector Type: None + External Reference Designator: External Monitor + External Connector Type: DB-15 female + Port Type: Video Port + +Handle 0x000E, DMI type 8, 9 bytes +Port Connector Information + Internal Reference Designator: Not Available + Internal Connector Type: None + External Reference Designator: Microphone Jack + External Connector Type: Mini Jack (headphones) + Port Type: Audio Port + +Handle 0x000F, DMI type 8, 9 bytes +Port Connector Information + Internal Reference Designator: Not Available + Internal Connector Type: None + External Reference Designator: Headphone Jack + External Connector Type: Mini Jack (headphones) + Port Type: Audio Port + +Handle 0x0010, DMI type 126, 9 bytes +Inactive + +Handle 0x0011, DMI type 126, 9 bytes +Inactive + +Handle 0x0012, DMI type 8, 9 bytes +Port Connector Information + Internal Reference Designator: Not Available + Internal Connector Type: None + External Reference Designator: Modem + External Connector Type: RJ-11 + Port Type: Modem Port + +Handle 0x0013, DMI type 8, 9 bytes +Port Connector Information + Internal Reference Designator: Not Available + Internal Connector Type: None + External Reference Designator: Ethernet + External Connector Type: RJ-45 + Port Type: Network Port + +Handle 0x0014, DMI type 8, 9 bytes +Port Connector Information + Internal Reference Designator: Not Available + Internal Connector Type: None + External Reference Designator: USB 1 + External Connector Type: Access Bus (USB) + Port Type: USB + +Handle 0x0015, DMI type 8, 9 bytes +Port Connector Information + Internal Reference Designator: Not Available + Internal Connector Type: None + External Reference Designator: USB 2 + External Connector Type: Access Bus (USB) + Port Type: USB + +Handle 0x0016, DMI type 8, 9 bytes +Port Connector Information + Internal Reference Designator: Not Available + Internal Connector Type: None + External Reference Designator: USB 3 + External Connector Type: Access Bus (USB) + Port Type: USB + +Handle 0x0017, DMI type 126, 9 bytes +Inactive + +Handle 0x0018, DMI type 126, 9 bytes +Inactive + +Handle 0x0019, DMI type 126, 9 bytes +Inactive + +Handle 0x001A, DMI type 126, 9 bytes +Inactive + +Handle 0x001B, DMI type 126, 9 bytes +Inactive + +Handle 0x001C, DMI type 126, 9 bytes +Inactive + +Handle 0x001D, DMI type 126, 9 bytes +Inactive + +Handle 0x001E, DMI type 126, 9 bytes +Inactive + +Handle 0x001F, DMI type 8, 9 bytes +Port Connector Information + Internal Reference Designator: Not Available + Internal Connector Type: None + External Reference Designator: IEEE1394 + External Connector Type: IEEE 1394 + Port Type: Firewire (IEEE P1394) + +Handle 0x0020, DMI type 9, 13 bytes +System Slot Information + Designation: ExpressCard Slot 1 + Type: x1 PCI Express + Current Usage: Available + Length: Other + ID: 0 + Characteristics: + Hot-plug devices are supported + +Handle 0x0021, DMI type 9, 13 bytes +System Slot Information + Designation: CardBus Slot 1 + Type: 32-bit PC Card (PCMCIA) + Current Usage: Available + Length: Other + ID: Adapter 1, Socket 0 + Characteristics: + 5.0 V is provided + 3.3 V is provided + PC Card-16 is supported + Cardbus is supported + Zoom Video is supported + Modem ring resume is supported + PME signal is supported + Hot-plug devices are supported + +Handle 0x0022, DMI type 126, 13 bytes +Inactive + +Handle 0x0023, DMI type 126, 13 bytes +Inactive + +Handle 0x0024, DMI type 126, 13 bytes